IP Library › Granted Patent US 12,670,060
Granted Patent B2
US 12,670,060 · App. 18/615,592 · Granted Jun 30, 2026

Dynamically configurable low density parity check code

Inventors: Phong S. Nguyen (Livermore, CA); Dung Viet Nguyen (San Jose, CA); James Fitzpatrick (Laguna Niguel, CA); Sivagnanam Parthasarathy (Carlsbad, CA); Zhengang Chen (San Jose, CA)
Assignee: Micron Technology, Inc.
G06F11/1004G06F11/1068
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Quick Facts
Patent No.
US 12,670,060
App. No.
18/615,592
Filed
Mar 25, 2024
Granted
Jun 30, 2026
Kind
B2
Art Unit
2111
USPC
714/764
Abstract

Input data is received for storage by a system. The input data is encoded using a low-density parity-check (LDPC) matrix to generate encoded data, wherein the LDPC matrix is selected from a plurality of LDPC matrices, each of the plurality of LDPC matrices having a common size and a unique degree distribution. The encoded data is then stored on a memory device of the system.

Claims (36)

1 . A system comprising:

a memory device; and

a processing device, operatively coupled with the memory device, to perform operations comprising:

receiving input data for storage by the system;

encoding the input data using a low-density parity-check (LDPC) matrix to generate encoded data, wherein the LDPC matrix is selected from a plurality of LDPC matrices, each of the plurality of LDPC matrices having a common size and a unique degree distribution, wherein the degree distribution indicates at least one of a number of columns an LDPC matrix or a number of rows in the LDPC matrix having a particular weight; and

storing the encoded data on the memory device.

2 . The system of claim 1 , wherein the processing device is to perform operations comprising:

determining one or more use case parameters;

determining one or more physical device parameters; and

selecting the LDPC matrix from the plurality of LDPC matrices based on the one or more use case parameters and one or more physical device parameters.

3 . The system of claim 2 , wherein the one or more use case parameters comprise one or more of a desired code rate, a number of program-erase (PE) cycles, or an operating temperature.

4 . The system of claim 2 , wherein the one or more physical device parameters comprise one or more of a wordline identifier, a block identifier, a page type, a die lot number, a die wafer number, or an intra-wafer die location.

5 . The system of claim 2 , wherein determining the one or more physical devices parameters comprises operations further comprising:

determining an intended location on the memory device where the encoded data is to be stored; and

determining the one or more physical device parameters associated with the intended location.

6 . The system of claim 2 , wherein the processing device is to perform operations further comprising:

configuring an LDPC encoder to use the LDPC matrix to encode the input data.

7 . The system of claim 2 , wherein the LDPC matrix is selected from the plurality of LDPC matrices based on its corresponding degree distribution.

8 . The system of claim 7 , wherein the corresponding degree distribution of the LDPC matrix is selected to provide improved performance with respect to trigger rate or reliability for certain usage conditions.

9 . A method comprising:

receiving input data for storage by a system;

encoding the input data using a low-density parity-check (LDPC) matrix to generate encoded data, wherein the LDPC matrix is selected from a plurality of LDPC matrices, each of the plurality of LDPC matrices having a common size and a unique degree distribution, wherein the degree distribution indicates at least one of a number of columns an LDPC matrix or a number of rows in the LDPC matrix having a particular weight; and

storing the encoded data on a memory device of the system.

10 . The method of claim 9 comprising:

determining one or more use case parameters;

determining one or more physical device parameters; and

selecting the LDPC matrix from the plurality of LDPC matrices based on the one or more use case parameters and one or more physical device parameters.

11 . The method of claim 10 , wherein the one or more use case parameters comprise one or more of a desired code rate, a number of program-erase (PE) cycles, or an operating temperature.

12 . The method of claim 10 , wherein the one or more physical device parameters comprise one or more of a wordline identifier, a block identifier, a page type, a die lot number, a die wafer number, or an intra-wafer die location.

13 . The method of claim 10 , wherein determining the one or more physical devices parameters comprises:

determining an intended location on the memory device where the encoded data is to be stored; and

determining the one or more physical device parameters associated with the intended location.

14 . The method of claim 10 comprising:

configuring an LDPC encoder to use the LDPC matrix to encode the input data.

15 . The method of claim 14 , wherein the LDPC matrix is selected from the plurality of LDPC matrices based on its corresponding degree distribution.

16 . The method of claim 15 wherein the corresponding degree distribution of the LDPC matrix is selected to provide improved performance with respect to trigger rate or reliability for certain usage conditions.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: NGUYEN, PHONG S.; NGUYEN, DUNG VIET; FITZPATRICK, JAMES; PARTHASARATHY, SIVAGNANAM; CHEN, ZHENGANG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 067340/0477 →
Continuity (2)
Provisional Application 63454847 · Mar 27, 2023
Related Publication 20240330105A1 · Oct 3, 2024
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