Adaptive countermeasure for bit leakage in lattice-based cryptography
A device may include a computer-readable memory and an integrated circuit including a processor configured to implement a cryptographic operation, wherein the cryptographic operation enables computation of a cryptographic result using a bit masking value y. The processor may be configured to access the computer-readable memory to determine a set of bit indexes, wherein each bit index in the set of bit indexes is associated with a bit value in the bit masking value y, for each bit index in the set of bit indexes, calculate an adaptive share value in which the bit value associated with the bit index is masked, and execute a cryptographic operation using the adaptive share value.
1 . A device comprising:
a computer-readable memory; and
an integrated circuit (IC) including a processor configured to implement a lattice-based digital signature scheme, wherein the lattice-based digital signature scheme enables computation of a digital signature of an input data value using a secret bit masking vector y and wherein different bits in the secret bit masking vector y have different levels of vulnerability to a side channel leakage attack conducted using a communication pin of the integrated circuit, the processor configured to:
access the computer-readable memory to determine a first number of shares,
decompose the secret bit masking vector y into a first set of share values, wherein a number of share values in the first set of share values is equal to the first number of shares,
access the computer-readable memory to determine a set of bit indexes, wherein each bit index in the set of bit indexes is associated with a bit value in the secret bit masking vector y,
determine selected bit indexes to be protected from the set of bit indexes;
determine a number of adaptive masking shares allocated for each selected bit index to be protected;
for each bit index in the set of bit indexes:
select a bit index from the set of bit indexes;
create, in the computer-readable memory, a plurality of adaptive masking shares corresponding to the number of adaptive masking shares allocated for the selected bit index;
initialize each adaptive masking share of the plurality of adaptive masking shares to an initial value;
determine an adaptive share value for each adaptive masking share of the plurality of adaptive masking shares based on the initial value and a random value r; and
mask the bit value associated with the selected bit index by adding the adaptive share value of each of the plurality of adaptive masking shares to the bit value to produce a protected masking vector, and
generate a cryptographic signature value associated with the input data value using the protected masking vector.
2 . The device of claim 1 , wherein the processor is further configured to:
access a list stored in the computer-readable memory to determine, for each bit index in the set of bit indexes, the number of adaptive shares.
3 . The device of claim 1 , wherein:
the initialized adaptive share is set to a zero value; and
the processor is configured to, for each bit index in the set of bit indexes, calculate the adaptive share value in which the bit value associated with the bit index is masked by:
determining the random value r, wherein the random value r has a value of 0 or 1;
multiplying the random value r by 2 i , wherein i is equal to the bit index, to generate the masking value; and
adding the initialized adaptive share and the masking value to generate the adaptive share value.
4 . The device of claim 1 , wherein the processor is configured to generate the cryptographic signature value associated with the input data value based on the first set of share values and the plurality of adaptive share values for the set of bit indexes.
5 . The device of claim 1 , wherein the lattice-based digital signature scheme is a Fiat-Shamir lattice-based cryptography scheme.
6 . The device of claim 5 , wherein the lattice-based cryptography scheme is a DILITHIUM digital signature scheme.
7 . The device of claim 6 , wherein the set of bit indexes includes an 8th bit of the secret bit masking vector y.
8 . A device comprising:
a computer-readable memory; and
an integrated circuit including a processor configured to implement a cryptographic operation, wherein the cryptographic operation enables computation of a cryptographic result using a bit masking value y, the processor being configured to:
access the computer-readable memory to determine a set of bit indexes, wherein each bit index in the set of bit indexes is associated with a bit value in the bit masking value y,
determine selected bit indexes to be protected from the set of bit indexes;
determine a number of adaptive masking shares allocated for each selected bit index to be protected;
for each bit index in the set of bit indexes,
select a bit index from the set of bit indexes;
create, in the computer-readable memory, a plurality of adaptive shares corresponding to the number of adaptive masking shares allocated for the selected bit index;
initialize each adaptive masking share of the plurality of adaptive masking shares allocated for the selected bit index to an initial value;
calculate an adaptive share value for each adaptive masking share of the plurality of adaptive masking shares allocated for the selected bit index based on the initial value and a random number;
mask the bit value associated with the selected bit index by adding the adaptive share value of each of the plurality of adaptive masking shares to the bit value to produce a protected masking value, and
execute a cryptographic operation using the protected masking value.
9 . The device of claim 8 , wherein the processor is further configured to:
access a list stored by the computer-readable memory to determine, for each bit index in the set of bit indexes, the number of adaptive masking shares.
10 . The device of claim 8 , wherein the initial value is set to a zero value and wherein the processor is configured to, for each bit index in the set of bit indexes, calculate the adaptive share value by:
determining the random value r, wherein the random value r has a value of 0 or 1;
multiplying the random value r by 2 i , wherein i is equal to the bit index, to generate a masking value; and
adding the initialized adaptive share and the masking value to generate the adaptive share value.
11 . The device of claim 8 , wherein executing the cryptographic operation includes generating a digital signature value using the protected masking value.
12 . The device of claim 8 , wherein the cryptographic operation includes a Fiat-Shamir lattice-based cryptography scheme.
13 . The device of claim 12 , wherein the cryptographic operation includes a DILITHIUM digital signature scheme.
14 . The device of claim 13 , wherein the set of bit indexes includes an 8th bit of the bit masking value y.
15 . A method operating a device to implement a lattice-based digital signature scheme, wherein the lattice-based digital signature scheme enables computation of a digital signature of an input data value using a bit masking value y and wherein different bits in the bit masking value y have different levels of vulnerability to a side channel leakage attack conducted using a communication pin of an integrated circuit, the method comprising including:
accessing a computer-readable memory to determine a first number of shares;
decomposing the bit masking value y into a first set of share values, wherein a number of share values in the first set of share values is equal to the first number of shares;
accessing the computer-readable memory to determine a set of bit indexes, wherein each bit index in the set of bit indexes is associated with a bit value in the bit masking value y;
determining selected bit indexes to be protected from the set of bit indexes;
determining a number of adaptive masking shares allocated for each selected bit index to be protected;
for each bit index in the set of bit indexes:
selecting a bit index from the set of bit indexes;
creating a plurality of adaptive masking shares corresponding to the number of adaptive masking shares allocated for the selected bit index;
calculating an adaptive share value for each adaptive masking share of the plurality of adaptive masking shares based on the initial value and a random value r; and
masking the bit value associated with the selected bit index by adding the adaptive share value of each of the plurality of adaptive masking shares to the bit value to produce a protected masking vector based on a predetermined number of adaptive shares; and
generating a digital signature value associated with the input data value using the protected masking vector.
16 . The method of claim 15 , further comprising:
accessing the computer-readable memory to determine, for each bit index in the set of bit indexes, a predetermined number of adaptive shares; and
for each bit index in the set of bit indexes, calculating a number of adaptive shares equal to the predetermined number of adaptive shares for the bit index.
17 . The method of claim 15 , further comprising, for each bit index in the set of bit indexes, calculating the adaptive share value in which the bit value associated with the bit index is masked by:
creating, in the computer-readable memory, an initialized adaptive share;
determining a random value r, wherein the random value r has a value of 0 or 1;
multiplying the random value r by 2 i , wherein i is equal to the bit index, to generate a masking value; and
adding the initialized adaptive share and the masking value to generate the adaptive share value.
18 . The method of claim 15 , further comprising generating the digital signature value associated with the input data value using each of the first set of share values and the adaptive share value.
19 . The method of claim 15 , further comprising determining that the lattice-based digital signature scheme is a DILITHIUM digital signature scheme.
20 . The method of claim 19 , further comprising determining that the set of bit indexes includes an 8th bit of the bit masking value y.