Epi barrier aligned backside contact
Embodiments disclosed herein include semiconductor devices and methods of forming such devices. In an embodiment, a semiconductor device comprises a vertical stack of semiconductor channels, a source on a first side of the vertical stack of semiconductor channels, and a drain on a second side of the vertical stack of semiconductor channels, In an embodiment, a metal is below the source and in direct contact with the source, where a centerline of the metal is substantially aligned with a centerline of the source.
1 . A semiconductor device, comprising:
a vertical stack of semiconductor channels;
a source on a first side of the vertical stack of semiconductor channels;
a drain on a second side of the vertical stack of semiconductor channels; and
a metal below the source and in direct contact with the source, wherein a centerline of the metal is substantially aligned with a centerline of the source, wherein the metal has an uppermost surface below a bottommost surface of the source, and wherein the metal has a lateral width across the centerline of the metal greater than a maximum lateral width of the source across the centerline of the source.
2 . The semiconductor device of claim 1 , wherein the semiconductor channels are nanowire or nanoribbon channels.
3 . The semiconductor device of claim 1 , further comprising:
a gate structure over and around the vertical stack of semiconductor channels.
4 . The semiconductor device of claim 1 , further comprising:
a dielectric over the source and the drain; and
an oxide over the dielectric.
5 . The semiconductor device of claim 4 , wherein the dielectric comprises silicon and nitrogen; silicon, carbon, and nitrogen; or silicon, oxygen, and nitrogen.
6 . The semiconductor device of claim 1 , wherein the metal comprises tungsten.
7 . The semiconductor device of claim 1 , wherein the source and the drain have scalloped sidewalls.
8 . The semiconductor device of claim 1 , wherein the source and the drain comprise an epitaxially grown semiconductor material.
9 . A method of forming an electronic device, comprising:
forming a fin over a substrate, wherein the fin comprises alternating layers of channel material and sacrificial material;
disposing a gate structure over the fin;
recessing the fin outside of the gate structure;
forming an epitaxial barrier layer on opposite sides of the fin;
forming a backside contact template at the bottom of the epitaxial barrier layer;
epitaxially growing a source region between the epitaxial barrier layer; and
replacing the backside contact template with a metal contact, wherein a centerline of the metal contact is substantially aligned with a centerline of the source region, wherein the metal contact has an uppermost surface below a bottommost surface of the source region, and wherein the metal contact has a lateral width across a centerline of the metal greater than a maximum lateral width of the source across a centerline of the source.
10 . The method of claim 9 , wherein the backside contact template comprises polysilicon.
11 . The method of claim 9 , further comprising:
disposing a dielectric layer over the source region.
12 . The method of claim 11 , wherein the dielectric layer comprises silicon and nitrogen; silicon, carbon and nitrogen; or silicon oxygen and nitrogen.
13 . The method of claim 9 , wherein the gate structure comprises polysilicon.
14 . The method of claim 13 , wherein the gate structure is replaced with a replacement metal gate structure after the source is formed.
15 . The method of claim 14 , wherein the sacrificial material is removed before the replacement metal gate structure is formed.
16 . The method of claim 9 , wherein replacing the backside contact template with a metal contact, comprises:
recessing a backside surface of the substrate to expose the backside contact template;
removing the backside contact template to form a cavity below the source; and
filling the cavity with the metal contact.
17 . The method of claim 9 , wherein the metal contact comprises tungsten.
18 . An electronic system, comprising:
a board;
a package substrate coupled to the board; and
a die coupled to the package substrate, wherein the die comprises:
a vertical stack of semiconductor channels;
a source on a first side of the vertical stack of semiconductor channels;
a drain on a second side of the vertical stack of semiconductor channels; and
a metal below the source and in direct contact with the source, wherein a centerline of the metal is substantially aligned with a centerline of the source, wherein the metal has an uppermost surface below a bottommost surface of the source, and wherein the metal has a lateral width across the centerline of the metal greater than a maximum lateral width of the source across the centerline of the source.