IP Library Granted Patent US 12,685,141
Granted Patent B2
US 12,685,141 · App. 18/136,888 · Granted Jul 14, 2026

Semiconductor structure and fabrication method thereof

Inventors: Da-Jun Lin (Kaohsiung City, TW); Chih-Wei Chang (Tainan City, TW); Fu-Yu Tsai (Tainan City, TW); Bin-Siang Tsai (Changhua County, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L21/7682H01L21/76832H01L23/53238
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Quick Facts
Patent No.
US 12,685,141
App. No.
18/136,888
Filed
Apr 20, 2023
Granted
Jul 14, 2026
Kind
B2
Art Unit
2899
USPC
257/758
Abstract

A semiconductor structure includes a substrate; a first dielectric layer on the substrate; an etch stop layer on the first dielectric layer; a second dielectric layer on the etch stop layer; a first conductor and a second conductor in the second dielectric layer, an air gap in the second dielectric layer and between the first conductor and the second conductor; and a low-polarity dielectric layer on a sidewall surface of the second dielectric layer within the air gap.

Claims (19)

1 . A semiconductor structure, comprising:

a substrate;

a first dielectric layer on the substrate;

an etch stop layer on the first dielectric layer;

a second dielectric layer on the etch stop layer;

a first conductor and a second conductor in the second dielectric layer;

an air gap in the second dielectric layer and between the first conductor and the second conductor;

a first low-polarity dielectric layer on a sidewall surface of the second dielectric layer within the air gap;

a second low-polarity dielectric layer disposed around the first conductor; and

a third low-polarity dielectric layer disposed around the second conductor.

2 . The semiconductor structure according to claim 1 , wherein the first dielectric layer is a silicon oxide layer and the second dielectric layer is a low-dielectric constant (low-k) material layer.

3 . The semiconductor structure according to claim 2 , wherein the low-k material layer comprises organo-silicate glass (OSG) based low-k dielectric layer.

4 . The semiconductor structure according to claim 1 , wherein the first low-polarity dielectric layer is a silylated surface layer.

5 . The semiconductor structure according to claim 1 , wherein the second and third low-polarity dielectric layers are silylated surface layers.

6 . The semiconductor structure according to claim 1 , wherein the second low-polarity dielectric layer is in direct contact with the first conductor, and the third low-polarity dielectric layer is in direct contact with the second conductor.

7 . The semiconductor structure according to claim 1 , wherein the first conductor and the second conductor comprise copper.

8 . The semiconductor structure according to claim 1 , wherein the air gap extends into the etch stop layer and the first dielectric layer.

9 . The semiconductor structure according to claim 8 further comprising:

a silylated oxide surface layer on a sidewall surface of the first dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 20, 2023
From: LIN, DA-JUN; CHANG, CHIH-WEI; TSAI, FU-YU; TSAI, BIN-SIANG
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 063383/0940 →
Priority Claims (1)
CN 202310311761.8 · Mar 28, 2023 · national
Continuity (1)
Related Publication 20240332066A1 · Oct 3, 2024
References Cited (10)
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