Vertically-stacked interdigitated metal-insulator-metal capacitor for sub-20 nm pitch
View Patent ↗Forming a vertically stacked interdigitated metal-insulator-metal capacitor includes forming a first set of connecting vias within a first dielectric layer disposed above a semiconductor substrate followed by deposition of a first conductive material above the first dielectric layer, the first conductive material fills the first set of connecting vias. A top portion of the first conductive material is patterned to form a first set of interdigitated electrodes. A remaining portion of the first conductive material below the first set of interdigitated electrodes includes a first metal plate. An insulating layer is conformally deposited above the first conductive material for electrically separating the first set of interdigitated electrodes and the first metal plate.
1 . A method of forming an interdigitated metal-insulator-metal capacitor, comprising:
forming a first set of connecting via openings within a dielectric layer disposed above a semiconductor substrate;
depositing a first conductive material to form:
a bottom portion of the first conductive material including bottom conductive vias formed in the via openings,
a middle portion of the first conductive material in contact with the bottom conductive vias and the dielectric layer, the middle potion formed as a first metal plate, and
a top portion of the first conductive material in contact with the middle portion;
patterning the top portion of the first conductive material to form a first set of interdigitated electrodes, wherein the first set of interdigitated electrodes extend upward from a top surface of the metal plate, and the bottom conductive vias extend downward from a bottom surface of the metal plate; and
conformally depositing an insulating layer above the first conductive material.
2 . The method of claim 1 , further comprising:
depositing a second conductive material above the insulating layer, wherein the depositing the second conductive material forms a second set of interdigitated electrodes interleaved with the first set of interdigitated electrodes; and
patterning a top portion of the second conductive material to form a second set of conductive vias, a remaining portion of the second conductive material below the second set of conductive vias comprising a second metal plate.
3 . The method of claim 1 , wherein the first set of conductive vias electrically connects the first metal plate to underlying structures disposed in the semiconductor substrate.
4 . The method of claim 1 , wherein the first set of interdigitated electrodes are in electrical communication with the first metal plate for increasing a charge collecting surface area of the interdigitated metal-insulator-metal capacitor.
5 . The method of claim 4 , wherein the second set of interdigitated electrodes are in electrical communication with the second metal plate for further increasing the charge collecting surface area of the interdigitated metal-insulator-metal capacitor.
6 . The method of claim 2 , wherein the second set of conductive vias electrically connects the second metal plate to subsequently formed structures.
7 . The method of claim 1 , wherein the first conductive material comprises at least one of cobalt, ruthenium, aluminum, titanium, and tungsten.
8 . The method of claim 2 , wherein the second conductive material comprises at least one of cobalt, ruthenium, aluminum, titanium, and tungsten.
9 . The method of claim 1 , wherein the insulating layer comprises a high-k dielectric material.
10 . The method of claim 9 , wherein the high-k dielectric material comprises at least one of aluminum oxide, hafnium oxide, and tantalum oxide.
11 . The method of claim 2 , wherein the first set of interdigitated electrodes and the second set of interdigitated electrodes have an aspect ratio of at least 1:1 for increasing a total capacitance of the metal-insulator-metal capacitor structure.
12 . The method of claim 1 , further comprising:
a second insulating layer disposed above the semiconductor substrate and below the first set of conductive vias.
13 . The method of claim 12 , wherein the second insulating layer comprises nitrogen-doped silicon carbide.