HBM silicon photonic TSV architecture for lookup computing AI accelerator
According to one general aspect, an apparatus may include a memory circuit die configured to store a lookup table that converts first data to second data. The apparatus may also include a logic circuit die comprising combinatorial logic circuits configured to receive the second data. The apparatus may further include an optical via coupled between the memory circuit die and the logical circuit die and configured to transfer second data between the memory circuit die and the logic circuit die.
1 . An apparatus comprising:
a first circuit die comprising a configurable logic circuit;
a second circuit die comprising one or more logic circuits configured to transform input data to first data, wherein the input data is received at the second circuit die; and
a communication path coupled between the first circuit die and the second circuit die and configured to transfer the first data between the first circuit die and the second circuit die;
wherein the apparatus is configured to determine a performance of the configurable logic circuit, and transfer, based on the performance, the first data, using the communication path, to the first circuit die, and process the first data using the configurable logic circuit.
2 . The apparatus of claim 1 , wherein the second circuit die comprises a driver circuit configured to receive the first data, wherein driver circuit is coupled to the communication path.
3 . The apparatus of claim 1 , wherein the first circuit die comprises:
a detector configured to detect data transmitted using the communication path; and
an amplifier circuit coupled between the detector and the configurable logic circuit.
4 . The apparatus of claim 1 , wherein the configurable logic circuit comprises at least one memory mat arranged in a memory bank; and
wherein the communication path is coupled to the memory bank.
5 . The apparatus of claim 1 , wherein the configurable logic circuit comprises a memory mat; and
wherein the communication path is communicatively coupled to the memory mat, wherein the memory mat is associated with a form of modulation such that a data transfer using the form of modulation is directed to the memory mat.
6 . The apparatus of claim 1 , wherein the second circuit die comprises
a scheduler circuit configured to coordinate data traffic using the communication path.
7 . The apparatus of claim 1 , wherein the communication path comprises a via; and
wherein the configurable logic circuit comprises a lookup table.