Effective synchronous gates for rapid single flux quantum logic
A superconducting multi-stage synchronous logic circuit structure includes a first clocked logic gate, a second clocked logic gate, and an unclocked logic gate. Each of the logic gates includes Josephson junctions. The first clocked logic gate has a single first clocked logic gate output; the second clocked logic gate has a single second clocked logic gate output. The unclocked logic gate has a first input connected in electrical communication with the first clocked logic gate output and has a second input connected in electrical communication with the second clocked logic gate output, and has a single output. The Josephson junctions of the unclocked logic gate are arranged such that, in a single clock cycle that drives the first clocked logic gate and the second clocked logic gate, the unclocked logic gate produces a single signal in response to the inputs of the first and second clocked logic gates.
1 . A superconducting multi-stage synchronous logic circuit structure, comprising:
a first clocked logic gate that comprises Josephson junctions and has a single first clocked logic gate output;
a second clocked logic gate that comprises Josephson junctions and has a single second clocked logic gate output; and
an unclocked logic gate that comprises Josephson junctions and that has a first input connected in electrical communication with the first clocked logic gate output and has a second input connected in electrical communication with the second clocked logic gate output, wherein the unclocked logic gate is a confluence buffer, and wherein the Josephson junctions of the unclocked logic gate are arranged such that, in a single clock cycle that drives the first clocked logic gate and the second clocked logic gate, the unclocked logic gate produces a single signal in response to the inputs of the first and second clocked logic gates.
2 . The structure of claim 1 , wherein the first clocked logic gate is a synchronous AND, and the second clocked logic gate also is a synchronous AND.
3 . The structure of claim 1 , wherein the first clocked logic gate is a synchronous OR, and the second clocked logic gate is a synchronous AND.
4 . The structure of claim 1 , wherein the first clocked logic gate is a synchronous OR, and the second clocked logic gate is a synchronous OR.
5 . The structure of claim 1 , wherein the first clocked logic gate is a synchronous XOR, and the second clocked logic gate is a synchronous AND.
6 . The structure of claim 1 , wherein the first clocked logic gate is a synchronous XOR, and the second clocked logic gate is a synchronous OR.
7 . The structure of claim 1 , wherein the first clocked logic gate is a synchronous XOR, and the second clocked logic gate is a synchronous XOR.
8 . The structure of claim 1 , wherein the first clocked logic gate is a synchronous inverter, and the second clocked logic gate is a synchronous AND.
9 . The structure of claim 1 , wherein the first clocked logic gate is a synchronous inverter, and the second clocked logic gate is a synchronous OR.
10 . The structure of claim 1 , wherein the first clocked logic gate is a synchronous inverter, and the second clocked logic gate is a synchronous XOR.
11 . The structure of claim 1 , wherein the first clocked logic gate is a synchronous D-flip-flop, and the second clocked logic gate is a synchronous AND.
12 . The structure of claim 1 , wherein the first clocked logic gate is a synchronous D-flip-flop, and the second clocked logic gate is a synchronous OR.
13 . The structure of claim 1 , wherein the first clocked logic gate is a synchronous D-flip-flop, and the second clocked logic gate is a synchronous XOR.
14 . The structure of claim 1 , wherein the unclocked logic gate is an asynchronous AND.
15 . The structure of claim 1 , further comprising a clock circuit that is configured to produce an SFQ clock pulse to each of the synchronous gates.
16 . The structure of claim 1 , wherein the first and second clocked logic gates together have three or more inputs.
17 . A method of operating a superconducting logic circuit structure, which includes first and second synchronous superconducting logic gates with their outputs tied to inputs of an asynchronous superconducting logic gate, the method comprising:
providing a plurality of inputs to the first and second synchronous superconducting logic gates, wherein the providing the plurality of inputs comprises providing three or more inputs after each of the first and second synchronous superconducting logic gates has received a first clock pulse and before each of the first and second synchronous superconducting logic gates receives a second clock pulse;
providing clock pulses to the first and second synchronous superconducting logic gates; and
receiving from an output of the asynchronous superconducting logic gate, without providing a clock pulse to the asynchronous superconducting logic gate, a signal dependent only on the plurality of inputs to the first and second synchronous superconducting logic gates.
18 . The method of claim 17 , wherein the signal is a Boolean value that depends on Boolean values of three or more inputs to the first and second synchronous superconducting logic gates.