IP Library Granted Patent US 12,725,549
Granted Patent B2
US 12,725,549 · App. 19/062,030 · Granted Sep 1, 2026

Electronic device

Inventors: Wei-Yu Su (Miaoli County, TW); Jui-Feng Ko (Miaoli County, TW); Geng-Fu Chang (Miaoli County, TW)
Assignee: Innolux Corporation
G09G3/20G09G2310/0291
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Quick Facts
Patent No.
US 12,725,549
App. No.
19/062,030
Granted
Sep 1, 2026
Kind
B2
Abstract

An electronic device is provided. The electronic device includes an electronic panel, a plurality of signal drivers, and a controller. The electronic panel includes a plurality of signal lines. The signal lines are divided into a plurality of signal line groups. The signal drivers are electrically connected to the signal line groups respectively. Two adjacent ones of the signal drivers are electrically connected to each other. The controller transmits a clock embedded digital signal to a first-level signal driver in the signal drivers. The signal drivers use point-to-point connection to sequentially transmit the clock embedded digital signal from the first-level signal driver to an N th -level signal driver in the signal drivers in a cascade manner, where N is greater than 1.

Claims (59)

1 . An electronic device, comprising:

a first electronic panel, comprising a plurality of signal lines, wherein the plurality of signal lines are divided into a plurality of signal line groups, the first electronic panel further comprising a pixel disposed on a first surface of the first electronic panel;

a plurality of first signal drivers, electrically connected to the plurality of signal line groups respectively, wherein two adjacent ones of the plurality of first signal drivers are electrically connected to each other; and

a controller, disposed on a circuit board, electrically connected to a first-level signal driver in the plurality of first signal drivers, and configured to transmit a clock embedded digital signal to the first-level signal driver,

wherein the plurality of first signal drivers use point-to-point connection to sequentially transmit the clock embedded digital signal from the first-level signal driver to an N th -level signal driver in the plurality of first signal drivers in a cascade manner, wherein N is greater than 1,

wherein the plurality of first signal drivers are electrically connected to the circuit board through chip-on-film packaging, and the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through traces on the circuit board, and

wherein the plurality of first signal drivers are electrically connected between a second surface of the first electronic panel and the circuit board through the chip-on-film packaging.

2 . The electronic device as claimed in claim 1 , wherein the clock embedded digital signal is a differential signal.

3 . The electronic device as claimed in claim 1 , wherein the first electronic panel further comprises:

a gate driver, wherein the controller further transmits a gate control signal to the gate driver.

4 . The electronic device as claimed in claim 3 , wherein

the controller is disposed on a circuit board, and

the controller is electrically connected to the gate driver and the first-level signal driver through a flat cable structure and traces on the circuit board.

5 . The electronic device as claimed in claim 1 , wherein

the controller is disposed on a circuit board,

the plurality of first signal drivers are electrically connected to the circuit board through chip-on-film packaging, and

the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through traces on the first electronic panel.

6 . The electronic device as claimed in claim 1 , wherein

the plurality of first signal drivers are disposed on the first electronic panel,

the controller is disposed on a circuit board, and

the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through a flat cable structure and traces on the circuit board.

7 . The electronic device as claimed in claim 1 , wherein

the plurality of first signal drivers are disposed on the first electronic panel,

the controller is disposed on a circuit board, and

the two adjacent ones of the plurality of first signal drivers are electrically connected to each other through traces on the first electronic panel.

8 . An electronic device, comprising:

a first electronic panel, comprising a plurality of signal lines, wherein the plurality of signal lines are divided into a plurality of signal line groups;

a plurality of first signal drivers, electrically connected to the plurality of signal line groups respectively, wherein two adjacent ones of the plurality of first signal drivers are electrically connected to each other;

a controller, electrically connected to a first-level signal driver in the plurality of first signal drivers, and configured to transmit a clock embedded digital signal to the first-level signal driver, wherein the controller is disposed on the first circuit board, wherein the plurality of first signal drivers use point-to-point connection to sequentially transmit the clock embedded digital signal from the first-level signal driver to an Nth-level signal driver in the plurality of first signal drivers in a cascade manner, wherein N is greater than 1,

a second electronic panel; and

a second circuit board, electrically connected to the second electronic panel,

wherein the first circuit board is electrically connected to the second circuit board through a signal transmission interface, and

wherein the Nth-level signal driver transmits the clock embedded digital signal to the second circuit board through the circuit board and the signal transmission interface.

9 . The electronic device as claimed in claim 8 , wherein the controller transmits a gate control signal to the second circuit board through the circuit board and the signal transmission interface.

10 . The electronic device as claimed in claim 8 , further comprising:

a plurality of second signal drivers, electrically connected to the second electronic panel, and two adjacent ones of the plurality of second signal drivers are electrically connected to each other,

wherein the plurality of second signal drivers are connected in the point-to-point connection to transmit the clock embedded digital signal.

11 . The electronic device as claimed in claim 10 , wherein a first-level signal driver in the plurality of second signal drivers receives the clock embedded digital signal through the signal transmission interface.

12 . The electronic device as claimed in claim 10 , wherein

the plurality of second signal drivers are electrically connected to the second circuit board through chip-on-film packaging, and

the two adjacent ones of the plurality of second signal drivers are electrically connected to each other through traces on the second circuit board.

13 . The electronic device as claimed in claim 10 , wherein

the plurality of second signal drivers are electrically connected to the second circuit board through chip-on-film packaging, and

the two adjacent ones of the plurality of second signal drivers are electrically connected to each other through traces on the second electronic panel.

14 . The electronic device as claimed in claim 8 , wherein

a plurality of second signal drivers are disposed on the second electronic panel, and

two adjacent ones of the plurality of second signal drivers are electrically connected to each other through a flat cable structure and traces on the second circuit board.

15 . The electronic device as claimed in claim 8 , wherein

a plurality of second signal drivers are disposed on the second electronic panel, and

two adjacent ones of the plurality of second signal drivers are electrically connected to each other through traces on the second electronic panel.

16 . The electronic device as claimed in claim 8 , wherein the first-level signal driver in the plurality of first signal drivers comprises:

a receiving circuit, configured to receive the clock embedded digital signal provided by the controller;

a transmitting circuit, electrically connected to the receiving circuit and a second-level signal driver in the plurality of first signal drivers; and

a latch, electrically connected to the receiving circuit, and configured to receive the clock embedded digital signal through the receiving circuit,

wherein after receiving a plurality of data signals of the clock embedded digital signal, the latch notifies the receiving circuit to provide the clock embedded digital signal to the transmitting circuit, and the transmitting circuit transmits the clock embedded digital signal to the second-level signal driver.

17 . The electronic device as claimed in claim 16 , wherein the plurality of data signals are respectively digital signals.

18 . The electronic device as claimed in claim 17 , wherein the first-level signal driver further comprises:

a digital-to-analog converter, electrically connected to the latch, and configured to convert the plurality of data signals into a plurality of data driving signals; and

an output buffer, electrically connected to the digital-to-analog converter, and configured to receive the plurality of data driving signals, and provide the plurality of data driving signals to a first signal line group in the plurality of signal line groups.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2025
From: SU, WEI-YU; KO, JUI-FENG; CHANG, GENG-FU
To: INNOLUX CORPORATION
Reel/Frame 070433/0060 →
Priority Claims (1)
CN 202410353048.4 · Mar 26, 2024 · national
Continuity (1)
Related Publication 20250308424A1 · Oct 2, 2025
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