Controlled doping in a gate dielectric layer
View Patent ↗The present disclosure describes method to form a semiconductor device having a gate dielectric layer with controlled doping. The method includes forming a gate dielectric layer on a fin structure, forming a diffusion barrier layer on the gate dielectric layer, and forming a dopant source layer on the diffusion barrier layer. The gate dielectric layer includes an interfacial layer on the fin structure and a high-k dielectric layer on the interfacial layer. A dopant of the dopant source layer diffuses into the gate dielectric layer. The method further includes doping a portion of the interfacial layer with the dopant and removing the dopant source layer. The portion of the interfacial layer is adjacent to the high-k dielectric layer.
1 . A semiconductor device, comprising:
a fin structure on a substrate;
an interfacial layer on the fin structure, wherein;
the interfacial layer comprises a top portion and an undoped bottom portion,
the top portion of the interfacial layer comprises a metal dopant,
the top portion has a first thickness, and
the undoped bottom portion has a second thickness greater than the first thickness;
a high-k dielectric layer on the top portion of the interfacial layer and comprising a high-k dielectric material; and
an intermixing layer on the high-k dielectric layer, wherein the intermixing layer is a mixture of the high-k dielectric layer and a diffusion barrier layer comprising nitrogen.
2 . The semiconductor device of claim 1 , wherein a bottom portion of the high-k dielectric layer adjacent to the top portion of the interfacial layer comprises the metal dopant, and wherein the metal dopant forms a dopant dipole at an interface of the interfacial layer and the high-k dielectric layer.
3 . The semiconductor device of claim 2 , wherein a ratio of a thickness of the bottom portion of the high-k dielectric layer to a thickness of the high-k dielectric layer ranges from about 0.03 to about 0.4.
4 . The semiconductor device of claim 2 , wherein a concentration of the metal dopant in the bottom portion of the high-k dielectric layer ranges from about 2 atomic percent about 55 atomic percent.
5 . The semiconductor device of claim 2 , wherein a ratio of a thickness of the top portion of the interfacial layer to a thickness of the interfacial layer ranges from about 0.03 to about 0.6.
6 . The semiconductor device of claim 1 , further comprising:
the diffusion barrier layer on the intermixing layer, wherein the diffusion barrier layer comprises the metal dopant; and
a gate electrode on the diffusion barrier layer.
7 . The semiconductor device of claim 1 , further comprising a gate electrode on the intermixing layer.
8 . The semiconductor device of claim 1 , wherein the intermixing layer comprises the high-k dielectric material, nitrogen, and at least one of titanium, tantalum, and aluminum.
9 . A semiconductor device, comprising:
a first gate dielectric layer on a first fin structure, wherein the first gate dielectric layer comprises a first interfacial layer and a first high-k dielectric layer, and wherein a top portion of the first interfacial layer comprises a dopant at a first concentration;
a second gate dielectric layer on a second fin structure, wherein the second gate dielectric layer comprises a second interfacial layer and a second high-k dielectric layer, and wherein a top portion of the second interfacial layer comprises the dopant at a second concentration different from the first concentration;
a first intermixing layer on the first high-k dielectric layer, wherein the first intermixing layer comprises the first high-k dielectric layer and a first diffusion barrier layer comprising nitrogen;
a second intermixing layer on the second high-k dielectric layer, wherein the second intermixing layer comprises the second high-k dielectric layer and a second diffusion barrier layer comprising nitrogen;
the first diffusion barrier layer on the first intermixing layer, wherein the first diffusion barrier layer has a first thickness; and
the second diffusion barrier layer on the second intermixing layer, wherein the second diffusion barrier layer has a second thickness different from the first thickness.
10 . The semiconductor device of claim 9 , wherein:
a bottom portion of the first high-k dielectric layer adjacent to the top portion of the first interfacial layer comprises the dopant and has a third thickness;
a bottom portion of the second high-k dielectric layer adjacent to the top portion of the second interfacial layer comprises the dopant and has a fourth thickness; and
the fourth thickness is different from the third thickness.
11 . The semiconductor device of claim 10 , wherein a concentration of the dopant in the bottom portion of the first high-k dielectric layer ranges from about 2 atomic percent to about 55 atomic percent.
12 . The semiconductor device of claim 9 , further comprising:
a gate electrode on the first diffusion barrier layer.
13 . The semiconductor device of claim 9 , further comprising a gate electrode on the first intermixing layer.
14 . The semiconductor device of claim 9 , wherein the first concentration is greater than the second concentration.
15 . The semiconductor device of claim 9 , wherein the first and second intermixing layers comprise a high-k dielectric material, nitrogen, and at least one of titanium, tantalum, and aluminum.
16 . A semiconductor device, comprising:
a first interfacial layer on a first fin structure, wherein the first interfacial layer comprises a first undoped portion and a first top portion doped with a dopant, and wherein the first interfacial layer has a first thickness and the first top portion has a second thickness;
a first high-k dielectric layer on the first interfacial layer, wherein the first high-k dielectric layer comprises a high-k dielectric material;
a second interfacial layer on a second fin structure, wherein the second interfacial layer comprises a second undoped portion and a second top portion doped with the dopant, and wherein the second interfacial layer has the first thickness and the second top portion has a third thickness different from the second thickness;
a second high-k dielectric layer on the second interfacial layer, wherein the second high-k dielectric layer comprises the high-k dielectric material; and
an intermixing layer on the first and second high-k dielectric layers, wherein the intermixing layer comprises the high-k dielectric material and a diffusion barrier layer comprising nitrogen.
17 . The semiconductor device of claim 16 , wherein:
the first high-k dielectric layer comprises a first bottom portion doped with the dopant;
the first bottom portion has a fourth thickness;
the second high-k dielectric layer comprises a second bottom portion doped with the dopant; and
the second bottom portion has a fifth thickness different from the fourth thickness.
18 . The semiconductor device of claim 16 , wherein a concentration of the dopant in the first and second bottom portions ranges from about 2 atomic percent to about 55 atomic percent.
19 . The semiconductor device of claim 16 , wherein the intermixing layer comprises a high-k dielectric material, nitrogen, and at least one of titanium, tantalum, and aluminum.
20 . The semiconductor device of claim 16 , further comprising a gate electrode on the intermixing layer.