Microelectronic structure comprising logic device and passive device with thinner Si layer
A microelectronic structure including a logic device and a passive device. The passive device includes a doped substrate, a silicide layer located on a backside surface of the doped substrate, and a metal plane located on a backside surface of the silicide layer.
1 . A microelectronic structure comprising:
a logic device; and
a passive device, wherein the passive device includes:
a doped substrate;
a plurality of source/drains;
a silicide layer located on a backside surface of the doped substrate, wherein the silicide layer forms a uniform plane that extends laterally across the plurality of source/drains, wherein the silicide layer is in continuous contact with the backside surface of the doped substrate as it extends across the plurality of source/drains;
a metal plane located on a backside surface of the silicide layer, wherein the metal plane forms a uniform plane that extends continuously across the surface of the silicide layer; and
a backside interlayer dielectric layer located on the backside surface of the metal plane.
2 . The microelectronic structure of claim 1 , wherein the doped substrate has a height/depth in the range of about 20 to 50 nm.
3 . The microelectronic structure of claim 2 , wherein the silicide layer and the metal plane have a combined height/depth in the range of about 10 to 30 nm.
4 . The microelectronic structure of claim 1 , wherein a combined height/depth of the doped substrate, the silicide layer, and the metal plane is in the range of about 30 to 80 nm.
5 . The microelectronic structure of claim 4 , wherein the silicide layer forms a single uniform layer across the backside surface of the doped substrate, and wherein the metal plane forms a single uniform layer across the backside surface of the silicide layer.
6 . The microelectronic structure of claim 5 , wherein the silicide layer and the metal plane increases the current flow through the doped substrate.
7 . The microelectronic structure of claim 1 , wherein the passive device is a diode.
8 . A microelectronic structure comprising:
a logic device that includes a backside contact; and
a passive device, wherein the passive device includes:
a doped substrate;
a plurality of source/drains;
a silicide layer located on a backside surface of the doped substrate, wherein the silicide layer forms a uniform plane that extends laterally across the plurality of source/drains, wherein the silicide layer is in continuous contact with the backside surface of the doped substrate as it extends across the plurality of source/drains;
a metal plane located on a backside surface of the silicide layer, wherein the metal plane forms a uniform plane that extends continuously across the surface of the silicide layer; and
a backside interlayer dielectric layer located on the backside surface of the metal plane.
9 . The microelectronic structure of claim 8 , wherein the doped substrate has a height/depth in the range of about 20 to 50 nm.
10 . The microelectronic structure of claim 9 , wherein the silicide layer and the metal plane have a combined height/depth in the range of about 10 to 30 nm.
11 . The microelectronic structure of claim 8 , wherein a combined height/depth of the doped substrate, the silicide layer, and the metal plane is in the range of about 30 to 80 nm.
12 . The microelectronic structure of claim 11 , wherein the silicide layer forms a single uniform layer across the backside surface of the doped substrate, and wherein the metal plane forms a single uniform layer across the backside surface of the silicide layer.
13 . The microelectronic structure of claim 12 , wherein the silicide layer and the metal plane increases the current flow through the doped substrate.
14 . The microelectronic structure of claim 11 , wherein the logic device further comprises:
a source/drain; and
a second silicide layer located on the backside surface of the source/drain.
15 . The microelectronic structure of claim 14 , wherein the backside contact is connected to a backside surface of the second silicide layer.
16 . The microelectronic structure of claim 15 , wherein the backside contact has a height/depth in the range of about 30 to 80 nm.
17 . The microelectronic structure of claim 16 , wherein the backside contact has a height/depth is substantially equal to the combined height/depth of the doped substrate, the silicide layer, and the metal plane.
18 . The microelectronic structure of claim 8 , wherein a backside surface of the backside contact of the logic device is substantially uniform/planar with the backside surface of the metal plane of the passive device.
19 . The microelectronic structure of claim 8 , wherein the passive device is a diode.
20 . A method comprising:
forming a logic device that includes a backside contact; and
forming a passive device, wherein the passive device includes:
a doped substrate;
a plurality of source/drains;
a silicide layer located on a backside surface of the doped substrate, wherein the silicide layer forms a uniform plane that extends laterally across the plurality of source/drains, wherein the silicide layer is in continuous contact with the backside surface of the doped substrate as it extends across the plurality of source/drains;
a metal plane located on a backside surface of the silicide layer, wherein a combined height/depth of the doped substrate, the silicide layer, and the metal plane is in the range of about 30 to 80 nm, wherein the metal plane forms a uniform plane that extends continuously across the surface of the silicide layer; and
a backside interlayer dielectric layer located on the backside surface of the metal plane.