Granted Patent B2

US 12,727,256 · App. 18/213,442 · Granted Sep 1, 2026

Inventors: Sagar Premnath Karalkar (Essex Junction, VT); Vishal Ganesan (Dresden, DE); Kyong Jin Hwang (Singapore, SG); Souvick Mitra (Essex Junction, VT)

Assignee: GlobalFoundries U.S. Inc.

H10D89/814

Abstract

Claims (46)

1 . A structure for an electrostatic discharge protection device, the structure comprising:

a semiconductor substrate;

a first shallow trench isolation region in the semiconductor substrate;

a first gate over the semiconductor substrate;

a second gate over the semiconductor substrate, the second gate adjacent to the first gate;

a source adjacent to the first gate, the source including a first well in the semiconductor substrate, a second well in the semiconductor substrate, a third well in the semiconductor substrate, and a first doped region, the first well and the first doped region having a first conductivity type, the second well having a second conductivity type opposite from the first conductivity type, the third well having the first conductivity type at a lower dopant concentration than the first well, the first well disposed between the third well and the first doped region, the first well having a corner that is disposed beneath the first shallow trench isolation region, the third well including a portion beneath the first well, the third well wrapping about the corner of the first well, the first doped region having a first portion that overlaps with the first well, and the first doped region having a second portion that overlaps with the second well; and

a drain adjacent to the second gate,

wherein the first gate and the second gate are laterally between the source and the drain.

2 . The structure of claim 1 wherein the first conductivity type is n-type, and the second conductivity type is p-type.

3 . The structure of claim 1 wherein the first well and the second well adjoin at an interface, and the first doped region overlaps with the interface.

4 . The structure of claim 3 wherein the first portion of the first doped region adjoins the first well on one side of the interface, and the second portion of the first doped region adjoins the second well on an opposite side of the interface.

5 . The structure of claim 1 further comprising:

a first terminal,

wherein the first gate, the second gate, and the source are coupled to the first terminal.

6 . The structure of claim 5 further comprising:

a second terminal,

wherein the drain is coupled to the second terminal.

7 . The structure of claim 6 wherein the first terminal is configured to tie the first gate, the second gate, and the source to ground, and the second terminal is an input/output terminal.

8 . The structure of claim 1 wherein the drain includes a doped region, and further comprising:

a second shallow trench isolation region disposed laterally between the doped region of the drain and the second gate.

9 . The structure of claim 1 wherein the semiconductor substrate has a top surface, the drain includes a doped region adjacent to the top surface, and further comprising:

a dielectric region disposed laterally between the doped region of the drain and the second gate, the dielectric region including a first portion above the top surface and a second portion below the top surface.

10 . The structure of claim 1 wherein the semiconductor substrate has a top surface, the drain includes a doped region, a first well in the semiconductor substrate, and a second well in the semiconductor substrate, the doped region of the drain is disposed adjacent to the top surface, and the first well of the drain is disposed between the doped region of the drain and the second well of the drain.

11 . The structure of claim 10 wherein the doped region of the drain has the first conductivity type, the first well of the drain has the first conductivity type at a lower dopant concentration than the doped region of the drain, and the second well of the drain has the first conductivity type at a lower dopant concentration than the first well of the drain.

12 . The structure of claim 1 further comprising:

a second doped region in the semiconductor substrate, the second doped region having the second conductivity type, and the second doped region positioned in a lateral direction between the first gate and the second gate.

13 . The structure of claim 12 further comprising:

a silicide-blocking layer extending from the first gate to the second gate, the silicide-blocking layer disposed over the second doped region, and the silicide-blocking layer comprising a dielectric material.

14 . The structure of claim 13 wherein the dielectric material of the silicide blocking layer fully overlaps with the second doped region such that the second doped region is electrically floating.

15 . The structure of claim 13 wherein the first gate and the second gate each include a gate conductor layer and a gate dielectric layer, and the gate dielectric layer comprises a material different than the dielectric material of the silicide-blocking layer.

16 . The structure of claim 12 further comprising:

a fourth well in the semiconductor substrate, the fourth well having the second conductivity type at a lower dopant concentration than the second doped region, and the fourth well surrounding the second doped region.

17 . The structure of claim 1 further comprising:

a fourth well in the semiconductor substrate, the fourth well having the second conductivity type at a lower dopant concentration than the second well,

wherein the fourth well is wrapped about a corner of the second well, the first gate overlaps with a portion of the second well, the first gate overlaps with a first portion of the fourth well, and the second gate overlaps with a second portion of the fourth well.

18 . The structure of claim 1 wherein the first gate is disposed over a portion of the second well.

19 . The structure of claim 17 further comprising:

a second doped region in the semiconductor substrate, the second doped region having the second conductivity type, and the second doped region positioned in a lateral direction between the first gate and the second gate; and

a dielectric layer extending from the first gate to the second gate, the dielectric layer fully overlapping with the second doped region such that the second doped region is electrically floating.

20 . A method of forming a structure for an electrostatic discharge protection device, the method comprising:

forming a first gate over a semiconductor substrate;

forming a shallow trench isolation region in the semiconductor substrate;

forming a second gate over the semiconductor substrate, wherein the second gate is disposed adjacent to the first gate;

forming a source adjacent to the first gate, wherein the source includes a first well in the semiconductor substrate, a second well in the semiconductor substrate, a third well in the semiconductor substrate, and a first doped region, the first well and the first doped region have a first conductivity type, the second well has a second conductivity type opposite from the first conductivity type, the third well has the first conductivity type at a lower dopant concentration than the first well, the first well is disposed between the third well and the first doped region, the first well has a corner that is disposed beneath the shallow trench isolation region, the third well includes a portion beneath the first well, the third well wrapping about the corner of the first well, the first doped region has a first portion that overlaps with the first well, and the first doped region has a second portion that overlaps with the second well; and

forming a drain adjacent to the second gate,

wherein the first gate and the second gate are laterally between the source and the drain.

Assignments (1)

Continuity (1)

References Cited (25)