Micro display device
A semiconductor device includes a substrate having a bonding area and a pad area, a first inter-metal dielectric (IMD) layer on the substrate, a metal interconnection in the first IMD layer, a first pad on the bonding area and connected to the metal interconnection, and a second pad on the pad area and connected to the metal interconnection. Preferably, the first pad includes a first portion connecting the metal interconnection and a second portion on the first portion, and the second pad includes a third portion connecting the metal interconnection and a fourth portion on the third portion, in which top surfaces of the second portion and the fourth portion are coplanar.
1 . A semiconductor device comprising:
a substrate comprising a bonding area and a pad area;
a first inter-metal dielectric (IMD) layer on the substrate;
a metal interconnection in the first IMD layer;
a second IMD layer on the first IMD layer;
a first bonding pad on the bonding area and connected to the metal interconnection, and wherein the first bonding pad comprise a first bottom portion connecting the metal interconnection and a first top portion on the first bottom portion, wherein a width of a top surface of the first bottom portion is less than a width of a bottom surface of the first top portion, and wherein a bottom surface of the first top portion directly contacts a top surface of the second IMD layer;
a second bonding pad on the pad area and connected to the metal interconnection; and
a third bonding pad on the bonding area and connected to the first bonding pad, wherein the third bonding pad directly contacts the first bonding pad and disposed above the first bonding pad.
2 . The semiconductor device of claim 1 , wherein the second bonding pad comprises:
a second bottom portion connecting the metal interconnection; and
a second top portion on the second bottom portion.
3 . The semiconductor device of claim 2 , wherein top surfaces of the first top portion and the second top portion are coplanar.
4 . The semiconductor device of claim 2 , wherein the second IMD layer around the first bottom portion and the second bottom portion, and further comprising:
a third IMD layer on the second IMD layer and around the first top portion and the second top portion.
5 . The semiconductor device of claim 4 , wherein the third bonding pad comprises:
a third bottom portion connecting the first top portion of the first bonding pad; and
a third top portion on the third bottom portion.
6 . The semiconductor device of claim 4 , wherein the first bonding pad and the third bonding pad comprise different materials.
7 . The semiconductor device of claim 1 , wherein the first bonding pad and the second bonding pad comprise same material.
8 . The semiconductor device of claim 1 , wherein the metal interconnection extends from the bonding area to the pad area.
9 . A semiconductor device, comprising:
a circuit area defined on a substrate;
a bonding area around the circuit area;
a pad area around the bonding area; and
a first bonding pad and a second bonding pad on the bonding area, wherein the first bonding pad and the second bonding pad comprise different shapes in a top view, and wherein the second bonding pad directly contacts the first bonding pad and disposed above the first bonding pad, and wherein the first bonding pad comprise a first bottom portion connecting the metal interconnection and a first top portion on the first bottom portion, wherein a width of a top surface of the first bottom portion is less than a width of a bottom surface of the first top portion, and wherein a bottom surface of the first top portion directly contacts a top surface of a second IMD layer.
10 . The semiconductor device of claim 9 , further comprising a sub-bonding area on the bonding area, wherein the first bonding pad and the second bonding pad are on the sub-bonding area.
11 . The semiconductor device of claim 10 , further comprising a third bonding pad on the pad area.
12 . The semiconductor device of claim 11 , wherein a distance between an edge of the sub-bonding area and an edge of the third bonding pad is between 0-8 microns.
13 . The semiconductor device of claim 10 , wherein a distance between an edge of the sub-bonding area and the circuit area is between 0-6 microns.
14 . The semiconductor device of claim 9 , wherein a distance between an edge of the first bonding pad and an edge of the second bonding pad is between 0-6 microns.
15 . The semiconductor device of claim 9 , wherein the first bonding pad and the second bonding pad are on different levels.
16 . The semiconductor device of claim 9 , wherein the first bonding pad comprises a square in a top view.
17 . The semiconductor device of claim 9 , wherein the second bonding pad comprises a hexagon in a top view.