IP Library › Granted Patent US 11,450,633
Granted Patent B2
US 11,450,633 · App. 16/781,937 · Granted Sep 20, 2022

Package structure of semiconductor device with improved bonding between the substrates

Inventors: Ming-Tse Lin (Hsinchu, TW); Chung-Hsing Kuo (Taipei, TW); Hui-Ling Chen (Kaohsiung, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L24/06
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,450,633
App. No.
16/781,937
Granted
Sep 20, 2022
Kind
B2
Abstract

A package structure of a semiconductor device includes a first substrate, a second substrate, and a bonding layer. The bonding layer bonds the first substrate and the second substrate. The bonding layer includes an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer. The outer bonding pad pattern surrounds the inner bonding pad pattern. A first bonding pad density of the outer bonding pad pattern is greater than a second bonding pad density of the inner bonding pad pattern.

Claims (18)

1. A package structure of a semiconductor device, comprising:

a first substrate;

a second substrate; and

a bonding layer bonding the first substrate and the second substrate, wherein the bonding layer comprises an inner bonding pad pattern and an outer bonding pad pattern formed in a dielectric layer, and the outer bonding pad pattern surrounds the inner bonding pad pattern,

wherein the outer bonding pad pattern is a dummy pattern, and the inner bonding pad pattern is connected between a circuit in the first substrate and a circuit in the second substrate,

wherein the inner bonding pad pattern comprises a plurality of first bonding pads arranged with a pitch between two adjacent first bonding pads in a vertical direction and a horizontal direction, the outer bonding pad pattern comprises a plurality of second bonding pads, and each of the first bonding pads has the same size as each of the second bonding pads, and

a density of the second bonding pads of the outer bonding pad pattern is greater than a density of the first bonding pads of the inner bonding pad pattern, and

a vertical pitch between two of the first bonding pads of the inner bonding pad pattern is greater than a vertical pitch between two of the second bonding pads of the outer bonding pad pattern,

the second bonding pads of the outer bonding pad pattern are distributed to form a plurality of pad rings surrounding the inner bonding pad pattern, and the second bonding pads of the plurality of pad rings are alternately shifted in the horizontal direction or the vertical direction.

2. The package structure of a semiconductor device according to claim 1 , wherein a first distance between the two adjacent second bonding pads in the outer bonding pad pattern at the first bonding pad density, a second distance between the two adjacent first bonding pads in the inner bonding pad pattern at the second bonding pad density, wherein the first distance is smaller than the second distance.

3. The package structure of a semiconductor device according to claim 1 , wherein the first substrate comprises a first bonding layer, the second substrate comprises a second bonding layer, and the first bonding layer and the second bonding layer are bonded together to form the bonding layer.

4. The package structure of a semiconductor device according to claim 1 , wherein the first bonding pads of the inner bonding pad pattern are uniformly distributed in a square region, a rectangular region, or a circular region.

5. The package structure of a semiconductor device according to claim 1 , wherein the outer bonding pad pattern is a right-angle quadrilateral, and each side of the right-angle quadrilateral comprises a plurality of bonding pad rows along the side.

6. The package structure of a semiconductor device according to claim 5 , wherein a distribution of the second bonding pads in each of the bonding pad rows is the same.

7. The package structure of a semiconductor device according to claim 5 , wherein a distribution of the second bonding pads in each of the bonding pad rows is different between two adjacent bonding pad rows.

8. The package structure of a semiconductor device according to claim 5 , wherein the second bonding pads of the outer bonding pad pattern are distributed to form at least two pad rings, wherein a pad distribution of an inner ring of the at least two pad rings comprises discontinuous regions at corners of the right-angle quadrilateral.

9. The package structure of a semiconductor device according to claim 8 , wherein the second bonding pads of the at least two pad rings is distributed to form at least two bonding pad rows on each side of the right-angle quadrilateral, and a length of each of the at least two bonding pad rows is equal to a length of the corresponding side.

10. The package structure of a semiconductor device according to claim 1 , wherein a geometric shape of the first bonding pads comprises circle, square, rectangle, hexagon, or polygon, and a geometric shape of the second bonding pads comprises circle, square, rectangle, hexagon, or polygon.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2020
From: LIN, MING-TSE; KUO, CHUNG-HSING; CHEN, HUI-LING
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 051718/0173 →
Priority Claims (1)
TW 108148392 · Dec 30, 2019 · national
Continuity (1)
Related Publication 20210202418A1 · Jul 1, 2021
Cited By (3)
US 12,309,921 US 12,400,944 US 12,532,758