Semiconductor device
View Patent ↗A semiconductor device according to an embodiment of the present disclosure includes: a first memory cell layer including a first selection line extending in a first direction, a second selection line extending in a second direction, and a first memory cell coupled to the first selection line and the second selection line; a second memory cell layer provided above the first memory cell layer, and including a third selection line extending in the first direction, a fourth selection line extending in the second direction, and a second memory cell coupled to the third selection line and the fourth selection line; and a first wiring layer provided between the first memory cell layer and the second memory cell layer and including a first metal wiring line.
1 . A semiconductor device comprising:
a first memory cell layer including a first selection line extending in a first direction, a second selection line extending in a second direction, and a first memory cell coupled to the first selection line and the second selection line;
a second memory cell layer provided above the first memory cell layer, and including a third selection line extending in the first direction, a fourth selection line extending in the second direction, and a second memory cell coupled to the third selection line and the fourth selection line;
a first wiring layer provided between the first memory cell layer and the second memory cell layer and including a first metal wiring line; and
a first via provided below the first wiring layer and configured by same material as the first metal wiring line, the first via coupling the first metal wiring line and the first selection line of the first memory cell layer to each other.
2 . The semiconductor device according to claim 1 , wherein
the first selection line in the first memory cell layer and the third selection line in the second memory cell layer are arranged at same position in a plane including the first direction and the second direction, and
the second selection line in the first memory cell layer and the fourth selection line in the second memory cell layer are arranged at same position in the plane including the first direction and the second direction.
3 . A semiconductor device comprising:
a first memory cell layer including a first selection line extending in a first direction, a second selection line extending in a second direction, and a first memory cell coupled to the first selection line and the second selection line;
a second memory cell layer provided above the first memory cell layer, and including a third selection line extending in the first direction, a fourth selection line extending in the second direction, and a second memory cell coupled to the third selection line and the fourth selection line;
a first wiring layer provided between the first memory cell layer and the second memory cell layer and including a first metal wiring line;
a first via provided below the first wiring layer and configured integrally with the first metal wiring line, the first via coupling the first metal wiring line and the first selection line of the first memory cell layer to each other;
a second wiring layer including a second metal wiring line provided below the first memory cell layer;
a second via provided between the first wiring layer and the second wiring layer and configured integrally with the first metal wiring line, the second via coupling the first metal wiring line and the second metal wiring line to each other; and
a drive circuit provided below the second wiring layer and being coupled to the second metal wiring line, the drive circuit driving the first selection line of the first memory cell layer.
4 . A semiconductor device comprising:
a first memory cell layer including a first selection line extending in a first direction, a second selection line extending in a second direction, and a first memory cell coupled to the first selection line and the second selection line;
a second memory cell layer provided above the first memory cell layer, and including a third selection line extending in the first direction, a fourth selection line extending in the second direction, and a second memory cell coupled to the third selection line and the fourth selection line;
a first wiring layer provided between the first memory cell layer and the second memory cell layer and including a first metal wiring line;
a first via provided below the first wiring layer and configured integrally with the first metal wiring line, the first via coupling the first metal wiring line and the first selection line of the first memory cell layer to each other;
a second wiring layer including a second metal wiring line provided above the second memory cell layer; and
a second via provided between the second wiring layer and the first wiring layer and configured integrally with the second metal wiring line, the second via coupling the second metal wiring line and the third selection line of the second memory cell layer to each other.
5 . The semiconductor device according to claim 4 , further comprising a third via provided between the second wiring layer and the first wiring layer and configured integrally with the second metal wiring line, the third via coupling the second metal wiring line and the first metal wiring line to each other.
6 . The semiconductor device according to claim 4 , further comprising:
a third via provided between the second wiring layer and the first wiring layer; and
a drive circuit provided below the first memory cell layer and driving the third selection line of the second memory cell layer, wherein
the first wiring layer includes a third metal wiring line coupled to the drive circuit, and
the third via is configured integrally with the second metal wiring line and couples the second metal wiring line and the third metal wiring line to each other.
7 . The semiconductor device according to claim 4 , wherein the second via provided between the second wiring layer and the first wiring layer and the first via provided below the first wiring layer are arranged at same position in a plane including the first direction and the second direction.
8 . The semiconductor device according to claim 7 , further comprising:
a third via provided below the first wiring layer; and
a fourth via provided between the second wiring layer and the first wiring layer, wherein
the first wiring layer includes a third metal wiring line,
the second wiring layer includes a fourth metal wiring line,
the third via is configured integrally with the third metal wiring line and couples the third metal wiring line and the second selection line to each other,
the fourth via is configured integrally with the fourth metal wiring line and couples the fourth metal wiring line and the fourth selection line to each other, and
the third via and the fourth via are arranged at same position in the plane including the first direction and the second direction.
9 . A semiconductor device comprising:
a first memory cell layer including a first selection line extending in a first direction, a second selection line extending in a second direction, and a first memory cell coupled to the first selection line and the second selection line;
a second memory cell layer provided above the first memory cell layer, and including a third selection line extending in the first direction, a fourth selection line extending in the second direction, and a second memory cell coupled to the third selection line and the fourth selection line; and
a first wiring layer provided between the first memory cell layer and the second memory cell layer and including a first metal wiring line, wherein
the first memory cell layer further includes a second metal wiring line extending in the first direction and a third memory cell coupled to the second selection line and the second metal wiring line, and
the second memory cell layer further includes a third metal wiring line extending in the first direction and a fourth memory cell coupled to the fourth selection line and the third metal wiring line.