Semiconductor device
A semiconductor device includes a plurality of first conductive lines in a first wiring layer, a plurality of second conductive lines in a second wiring layer, and a plurality of memory cells between the first and second conductive lines in a first direction in a first region. A plurality of third conductive lines in the first wiring layer, a plurality of fourth conductive lines in the second wiring, and a plurality of first memory lines are in a second region. The third conductive lines extends in a second direction and are spaced from each other in a third direction. The fourth conductive lines extend in the second direction and are spaced in the third direction. The first memory lines are between the third conductive lines and the fourth conductive lines in the first direction. The first memory lines comprise the same materials as the memory cells.
1. A semiconductor device, comprising:
a first region on a substrate;
a second region on the substrate;
a first wiring layer on the substrate in both the first region and the second region;
a second wiring layer on the substrate in both the first region and the second region;
a first memory cell layer between the first and second wiring layers in a first direction orthogonal to the substrate;
a plurality of first conductive lines in the first wiring layer in the first region and extending in a second direction that is parallel to the substrate, the first conductive lines being spaced from each other in a third direction crossing the second direction and parallel to the substrate;
a plurality of second conductive lines in the second wiring layer in the first region and extending in the third direction and spaced from each other in the second direction;
a first plurality of memory cells in the first memory cell layer in the first region respectively between a first conductive line and a second conductive line at a crossing point of the first conductive line and the second conductive line;
a plurality of third conductive lines in the first wiring layer in the second region and extending in the second direction and spaced from each other in the third direction;
a plurality of fourth conductive lines in the second wiring layer in the second region and extending in the second direction and spaced from each other in the third direction;
a first plurality of memory lines in the first memory cell layer in the second region respectively between a third conductive line and a fourth conductive line, the memory lines extending coextensively in the second direction with the third and fourth conductive lines, wherein
the memory cells and the memory lines in the first memory cell layer are comprised of same materials, and
a capacitor element is formed in the second region by the plurality of third conductive lines, the plurality of fourth conductive lines, and the first plurality of memory lines.
2. The semiconductor device according to claim 1 , further comprising:
a first connection line in the first wiring layer in the second region and extending in the third direction, ends of a first subset of the plurality of third conductive lines being connected to the first connection line; and
a second connection line in the first wiring layer in the second region and extending in the third direction, the second connection line being spaced from the first connection line in the second direction, ends of a second subset of the plurality of third conductive lines being connected to the second connection line, wherein
the capacitor element comprises an interdigitated comb structure.
3. The semiconductor device according to claim 2 , further comprising:
a test circuit having a first node electrically connected to the first subset and a second node electrically connected to the second subset, the test circuit being configured to detect a short circuit failure between the first and second subsets.
4. The semiconductor device according to claim 1 , wherein an electrical resistivity of each memory line is less than an electrical resistivity of an insulating film between adjacent memory lines in the first memory cell layer in the second region.
5. The semiconductor device according to claim 4 , further comprising:
a write circuit having a first node selectively connectable to the plurality of third conductive lines and a second node selectively connectable to the plurality of fourth conductive lines.
6. The semiconductor device according to claim 5 , wherein the electrical resistivity of each memory line is set according to a writing operation by the writing circuit that applies a write voltage across a corresponding third conductive line and a corresponding fourth conductive line.
7. The semiconductor device according to claim 1 , further comprising:
a first connection line in the second wiring layer in the second region and extending in the third direction, ends of a first subset of the plurality of fourth conductive lines being connected to the first connection line; and
a second connection line in the second wiring layer in the second region and extending in the third direction, the second connection line being spaced from the first connection line in the second direction, ends of a second subset of the plurality of fourth conductive lines being connected to the second connection line, wherein
the capacitor element comprises an interdigitated comb structure.
8. The semiconductor device according to claim 1 , further comprising:
a second memory cell layer on the substrate between the first and second wiring layers in the first direction;
a second plurality of memory cells in the second memory cell layer in the first region;
a second plurality of memory lines in the second memory cell layer in the second region;
a plurality of fifth conductive lines in a third wiring layer between the first and second wiring layers in the first region; and
a plurality of sixth conductive lines in the third wiring layer in the second region, wherein
the memory cells and the memory lines in the second memory cell layer are comprised of same materials.
9. The semiconductor device according to claim 8 , further comprising:
an interlayer insulating film between the first and second memory cell layers in the first direction.
10. The semiconductor device according to claim 1 , further comprising:
a second memory cell layer on the substrate above the first memory cell layer in the first direction;
a third wiring layer on the substrate above the second memory cell layer in the first direction;
a plurality of fifth conductive lines in the third wiring layer in the first region;
a plurality of sixth conductive lines in the third wiring layer in the second region;
a second plurality of memory cells in the second memory cell layer in the first region;
a second plurality of memory lines in the second memory cell layer in the second region, wherein
the memory cells and the memory lines in the second memory cell layer are comprised of same materials.
11. The semiconductor device according to claim 10 , wherein
the fifth conductive lines extend in the second direction and are spaced from each other in the third direction,
the second plurality of memory cells are each electrically connected between a fifth conductive line and a second conductive line,
the sixth conductive lines extend in the second direction and are spaced from each other in the third direction, and
the second plurality of memory lines are electrically connected between a sixth conductive line and a fourth conductive line.
12. The semiconductor device according to claim 10 , further comprising:
an interlayer insulating film between the first and second memory cell layers in the first direction.
13. The semiconductor device according to claim 1 , further comprising:
an insulating material between the plurality of first conductive lines and the plurality of third conductive lines.
14. The semiconductor device according to claim 1 , wherein a width of each first conductive line in the third direction is equal to a width of each third conductive line in the third direction.
15. The semiconductor device according to claim 1 , wherein a spacing between adjacent first conductive lines in the third direction is different from a spacing between adjacent third conductive lines in the third direction.
16. The semiconductor device according to claim 1 , further comprising:
a plurality of capacitor elements formed in the second region by the plurality of third conductive lines, the plurality of fourth conductive lines, and the first plurality of memory lines;
a test circuit configured to test the plurality of capacitor elements for short circuit failures; and
a selector configured to receive a selection signal from the test circuit and select a capacitor element from the plurality of capacitor elements without a short circuit failure.
17. A semiconductor device, comprising:
a memory region on a substrate;
a peripheral region on the substrate adjacent to the memory region;
a plurality of bit lines in a first wiring level in the memory region, the bit lines extending in a first direction and spaced from each other in a second direction;
a plurality of word lines in a second wiring level in the memory region, the word lines extending in the second direction and spaced from each other in the first direction;
a first plurality of memory cells between the first and second wiring levels in the memory region in a third direction orthogonal to the substrate, each memory cell respectively being at a crossing point of a bit line and a word line;
a plurality of first conductive lines in the first wiring level in the peripheral region, the first conductive lines extending in the first direction and spaced from each other in the second direction;
a plurality of second conductive lines in the second wiring level in the peripheral region, the second conductive lines extending in the first direction and spaced from each other in the second direction;
a first plurality of memory lines in the peripheral region between the first and second wiring levels in the third direction, each memory line being between a third conductive line and a fourth conductive line and extending coextensively in the first direction with the third and fourth conductive lines, wherein
the memory cells and the memory lines are comprised of same materials, and
a capacitor element is formed in the peripheral region by the plurality of first conductive lines, the plurality of second conductive lines, and the first plurality of memory lines.
18. The semiconductor device according to claim 17 , further comprising:
a first connection line in the second wiring level in the peripheral region and extending in the second direction, ends of a first subset of the plurality of second conductive lines being connected to the first connection line; and
a second connection line in the second wiring level in the peripheral region and extending in the second direction, the second connection line being spaced from the first connection line in the first direction, ends of a second subset of the plurality of second conductive lines being connected to the second connection line, wherein
the capacitor element comprises an interdigitated comb structure.
19. The semiconductor device according to claim 18 , wherein every second conductive line in the first subset is adjacent to a second conductive line in the second subset.
20. The semiconductor device according to claim 17 , further comprising:
a second plurality of memory cells in the memory region above the second wiring level in the third direction.