Semiconductor packages and methods of forming the same
A method includes bonding a first semiconductor die to a semiconductor substrate; bonding a second semiconductor die to the semiconductor substrate, wherein the second semiconductor die is laterally separated from the first semiconductor die by a gap; filling the gap between the first semiconductor die and the second semiconductor die with a metal material to form a thermally conductive region; and depositing a first dielectric layer over the first semiconductor die, the second semiconductor die, and the thermally conductive region.
1 . A method comprising:
bonding a first semiconductor die to a semiconductor substrate;
bonding a second semiconductor die to the semiconductor substrate, wherein the second semiconductor die is laterally separated from the first semiconductor die by a gap;
filling the gap between the first semiconductor die and the second semiconductor die with a metal material to form a thermally conductive region;
removing a portion of the metal material that is adjacent a sidewall of the first semiconductor die to form a recess;
filling the recess with a dielectric material; and
depositing a first dielectric layer over the first semiconductor die, the second semiconductor die, and the thermally conductive region.
2 . The method of claim 1 , wherein bonding the first semiconductor die to the semiconductor substrate comprises dielectric-to-dielectric bonding and metal-to-metal bonding.
3 . The method of claim 1 , wherein the first semiconductor die is a dummy die.
4 . The method of claim 1 , wherein filling the gap with the metal material comprises depositing a barrier layer and depositing copper over the barrier layer.
5 . The method of claim 1 further comprising forming a thermal interconnect structure over the first semiconductor die, the second semiconductor die, and the metal material, wherein forming the thermal interconnect structure comprises:
depositing a second dielectric layer over the first semiconductor die, the second semiconductor die, and the metal material; and
forming a plurality of metal features within the second dielectric layer, wherein the plurality of metal features physically contact the first semiconductor die, the second semiconductor die, and the metal material.
6 . The method of claim 1 further comprising, before filling the gap with the metal material, conformally depositing a third dielectric layer on top surfaces and sidewalls of the first semiconductor die and the second semiconductor die.
7 . The method of claim 4 , wherein the barrier layer comprises silicon nitride.
8 . A method comprising:
bonding a plurality of first semiconductor devices to a first package region of a substrate;
bonding a plurality of second semiconductor devices to a second package region of the substrate, wherein a scribe region separates the first package region from the second package region;
depositing a metal fill material over the substrate, the plurality of first semiconductor devices, and the plurality of second semiconductor devices, wherein the metal fill material surrounds each of the first semiconductor devices and each of the second semiconductor devices, wherein the metal fill material is deposited within the scribe region;
removing portions of the metal fill material from the scribe region; and
after removing portions of the metal fill material, depositing a first dielectric material in the scribe region, wherein the first dielectric material separates a first semiconductor device from a second semiconductor device.
9 . The method of claim 8 further comprising, before depositing the metal fill material over the substrate, depositing a sacrificial material in the scribe region.
10 . The method of claim 8 , wherein the first dielectric material is a spin-on-glass.
11 . The method of claim 8 , wherein the first dielectric material is a molding material.
12 . The method of claim 8 further comprising performing a singulation process through the first dielectric material and the substrate along the scribe region.
13 . The method of claim 8 , wherein the metal fill material is electrically isolated from the plurality of first semiconductor devices and the plurality of second semiconductor devices.
14 . The method of claim 8 further comprising, before depositing the metal fill material, depositing a conformal barrier layer over the substrate, the plurality of first semiconductor devices, and the plurality of second semiconductor devices.
15 . The method of claim 8 , wherein the first dielectric material extends farther from the substrate than the metal fill material.
16 . A method comprising:
bonding a plurality of semiconductor devices to an interposer;
forming a metallic material over the interposer, wherein the metallic material laterally separates neighboring semiconductor devices of the plurality of semiconductor devices;
removing the metallic material from between at least two neighboring semiconductor devices of the plurality of semiconductor devices;
after removing the metallic material, forming a dielectric material over the interposer, wherein the dielectric material laterally encircles a collective set of semiconductor devices of the plurality of semiconductor devices; and
attaching a support substrate over the plurality of semiconductor devices, wherein sidewalls of the support substrate, sidewalls of the dielectric material, and sidewalls of the interposer are coplanar.
17 . The method of claim 16 , wherein the metallic material is separated from the semiconductor devices of the plurality of semiconductor devices by a dielectric layer.
18 . The method of claim 16 , wherein a top surface of the dielectric material is farther from the interposer than a top surface of the metallic material.
19 . The method of claim 16 further comprising forming a thermal interconnect structure over the plurality of semiconductor devices, wherein the support substrate is attached to the thermal interconnect structure.
20 . The method of claim 16 further comprising attaching the interposer to a package substrate using a plurality of conductive connectors.