Semiconductor package including interposer
A semiconductor package includes an interposer including a base layer and a plurality of interposer through-electrodes penetrating the base layer; at least one stacked structure attached to the interposer and including a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, and a chip molding layer on a side surface of the plurality of second semiconductor chips; a plurality of third semiconductor chips attached to the interposer adjacent the at least one stacked structure; and a package molding layer extending around the at least one stacked structure and the plurality of third semiconductor chips on the interposer.
1 . A semiconductor package comprising:
an interposer comprising a base layer and a plurality of through-electrodes penetrating the base layer;
at least one stacked structure attached to the interposer, the at least one stacked structure comprising a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, and a chip molding layer on a side surface of the plurality of second semiconductor chips, the plurality of second semiconductor chips comprise high-bandwidth memory (HBM);
a plurality of third semiconductor chips attached to the interposer adjacent the at least one stacked structure; and
a package molding layer extending around the at least one stacked structure and the plurality of third semiconductor chips, wherein
the plurality of third semiconductor chips comprise a first chip group and a second chip group,
the at least one stacked structure is between the first chip group and the second chip group,
the first chip group and the second chip group comprise a plurality of functional blocks of central processing unit (CPU), graphics processing unit (GPU), and/or application-specific integrated circuit (ASIC) processing circuitry of one system-on-chip (SoC).
2 . The semiconductor package of claim 1 , wherein the interposer comprises a pair of first edges opposite to each other in a first direction and a pair of second edges opposite to each other in a second direction orthogonal to the first direction,
the first chip group is adjacent to one of the first edges, and the second chip group is adjacent to the other one of the first edges, and
the first chip group, the at least one stacked structure, and the second chip group are sequentially arranged along the first direction.
3 . The semiconductor package of claim 2 , wherein the first chip group includes at least two different semiconductor chips comprising respective functional blocks of the plurality of functional blocks, and the second chip group includes at least two different semiconductor chips comprising respective functional blocks of the plurality of functional blocks, and
the semiconductor chips in the first chip group are arranged in a row adjacent to one of the first edges, and the semiconductor chips in the second chip group are arranged in a row adjacent to the other one of the first edges.
4 . The semiconductor package of claim 2 , wherein the plurality of third semiconductor chips include at least two main semiconductor chips having a plurality of functional blocks and at least one chiplet having one functional block.
5 . The semiconductor package of claim 4 , wherein the at least one chiplet in the first chip group and the at least one chiplet in the second chip group are adjacent to a same one of the second edges.
6 . The semiconductor package of claim 4 , wherein the at least one chiplet in the first chip group is adjacent to one of the second edges and the at least one chiplet in the second chip group is adjacent to the other one of the second edges.
7 . The semiconductor package of claim 2 , wherein a side surface of the at least one stacked structure adjacent to one of the second edges is not closer to the one of the second edges than a side surface of a third semiconductor chip adjacent to the one of the second edges.
8 . The semiconductor package of claim 7 , wherein the side surface of the at least one stacked structure and the side surface of the third semiconductor chip are equidistant from the one of the second edges.
9 . The semiconductor package of claim 7 , wherein the side surface of the third semiconductor chip and the side surface of the at least one stacked structure are not equidistant from the one of the second edges.
10 . The semiconductor package of claim 1 , wherein each of the first chip group, the second chip group, and the at least one stacked structure has a rectangular footprint.
11 . A semiconductor package comprising:
an interposer comprising a base layer and a plurality of through-electrodes penetrating the base layer, the base layer comprising silicon, and the interposer having a pair of first edges opposite to each other in a first direction and a pair of second edges opposite to each other in a second direction orthogonal to the first direction;
a stacked structure group attached to the interposer, the stacked structure group comprising a plurality of stacked structures, each stacked structure comprising a first semiconductor chip, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip, and a chip molding layer on a side surface of the plurality of second semiconductor chips;
a plurality of third semiconductor chips attached to the interposer adjacent the stacked structure group, one of the plurality of third semiconductor chips being longer, in the second direction, than the first semiconductor chips and the pluralities of second semiconductor chips of the plurality of stacked structures; and
a package molding layer on the interposer, the package molding layer extending around the stacked structure group and the plurality of third semiconductor chips to form a molding interface with the chip molding layer,
wherein the plurality of third semiconductor chips comprise a first chip group arranged in a row along one of the first edges, and a second chip group arranged in a row along the other one of the first edges, and
wherein the stacked structure group is spaced apart from each of the first edges.
12 . The semiconductor package of claim 11 , wherein the first chip group, the stacked structure group, and the second chip group are sequentially arranged along the first direction.
13 . The semiconductor package of claim 11 , wherein the molding interface is not closer to one of the second edges than a side surface of the third semiconductor chip adjacent to the one of the second edges.
14 . The semiconductor package of claim 11 , wherein the chip molding layer has a first thickness in the second direction from a side surface of the plurality of second semiconductor chips, and
the package molding layer has a second thickness that is greater than the first thickness in the second direction.
15 . The semiconductor package of claim 14 , wherein the package molding layer has a third thickness in the second direction from a side surface of the stacked structure group to one of the second edges,
wherein the third thickness is greater than or equal to the second thickness.
16 . The semiconductor package of claim 11 , wherein the plurality of third semiconductor chips include a main semiconductor chip having a plurality of functional blocks and a chiplet having one functional block,
wherein the main semiconductor chip is electrically connected to the chiplet through the interposer and is configured to function as one System on Chip (SoC).
17 . The semiconductor package of claim 16 , wherein the first chip group includes a dummy chip that is adjacent to one of the second edges, and a chiplet that is adjacent the other one of the second edges,
wherein the second chip group includes a dummy chip that is adjacent to one of the second edges and a chiplet that is adjacent to the other one of the second edges, and
wherein the dummy chip in each of the first chip group and the second chip group does not include a semiconductor device.
18 . A semiconductor package comprising:
a package base substrate;
a silicon interposer attached to the package base substrate, the silicon interposer comprising a base layer and a plurality of through-electrodes penetrating the base layer, and having a pair of first edges opposite to each other in a first direction and a pair of second edges opposite to each other in a second direction orthogonal to the first direction;
a stacked structure group attached to the silicon interposer, the stacked structure group comprising a plurality of stacked structures, each stacked structure comprising a first semiconductor chip including a first semiconductor substrate and a plurality of first through-electrodes penetrating the first semiconductor substrate, a plurality of second semiconductor chips sequentially stacked on the first semiconductor chip and including a second semiconductor substrate and a plurality of second through-electrodes penetrating the second semiconductor substrate and electrically connected to the plurality of first through-electrodes, and a chip molding layer on an upper surface of the first semiconductor chip and a side surface of the plurality of second semiconductor chips;
a plurality of third semiconductor chips attached to the silicon interposer adjacent the stacked structure group; and
a package molding layer on the silicon interposer, the package molding layer extending around the stacked structure group and the plurality of third semiconductor chips to form a molding interface with the chip molding layer,
wherein the plurality of third semiconductor chips comprise a first chip group arranged in a row along one of the first edges, and a second chip group arranged in a row along the other one of the first edges,
wherein the stacked structure group is spaced apart from each of the first edges,
the chip molding layer has a first thickness in the second direction from a side surface of the plurality of second semiconductor chips toward one of the second edges, the package molding layer has a second thickness in the second direction between the side surface of the plurality of second semiconductor chips and the one of the second edges, and the second thickness is at least twice the first thickness, and
a side surface of the stacked structure group adjacent to one of the second edges is not closer to the one of the second edges than a side surface of the third semiconductor chip adjacent to the one of the second edges.
19 . The semiconductor package of claim 18 , wherein the first semiconductor chip is an HBM control die, the second semiconductor chip is a DRAM die, and
at least one of the plurality of third semiconductor chips has a plurality of functional blocks, and at least one of the plurality of third semiconductor chips has one functional block.
20 . The semiconductor package of claim 18 , wherein the first thickness is from about 150 μm to about 400 μm, and
the second thickness is from about 500 μm to about 1000 μm.