Semiconductor package including a pad comprising a connection portion connecting a first and second pad portions
A semiconductor package includes a redistribution structure in which redistribution layers and insulating layers are alternately stacked. A semiconductor chip is electrically connected to the redistribution layers, and bumps are electrically connected to the redistribution layers and arranged on one surface of the redistribution structure. The redistribution layers include pads arranged to face the bumps, and each of the pads includes a first pad portion offset from a center of each of the pads in a first direction, a second pad portion offset from the center of each of the pads in a second direction, and a connection portion connecting the first and second pad portions. The connection portion includes a protruding portion that defines a first recessed region recessed adjacent to the first pad portion and a second recessed region recessed adjacent to the second pad portion.
1 . A semiconductor package comprising:
a redistribution structure comprising at least one redistribution layer and at least one insulating layer alternately stacked;
a semiconductor chip electrically connected to the at least one redistribution layer; and
a plurality of bumps electrically connected to the at least one redistribution layer and arranged on a first surface of the redistribution structure,
wherein the at least one redistribution layer comprises a plurality of pads arranged to face the plurality of bumps, and
wherein each pad comprises:
a first pad portion offset from a center of the pad in a first direction and arranged to face one of the plurality of bumps;
a second pad portion offset from the center of the pad in a second direction different from the first direction; and
a connection portion connecting the first and second pad portions, wherein the connection portion comprises a protruding portion that defines a first recessed region adjacent to the first pad portion and a second recessed region adjacent to the second pad portion.
2 . The semiconductor package of claim 1 , wherein a width of the protruding portion is greater than a width of either the first or second recessed regions.
3 . The semiconductor package of claim 2 , wherein the width of the protruding portion is smaller than a width of the first pad portion.
4 . The semiconductor package of claim 2 , wherein the protruding portion comprises an edge facing the first pad portion, and wherein an angle formed between the edge of the protruding portion and the first direction is less than 90 degrees.
5 . The semiconductor package of claim 1 , further comprising a solder mask layer covering a portion of each of the plurality of pads,
wherein an area of the solder mask layer covering the second pad portion of each of the plurality of pads is greater than an area of the solder mask layer covering the first pad portion of each of the plurality of pads.
6 . The semiconductor package of claim 1 , further comprising a plurality of Under Bump Metallurgy (UBM) structures, each UBM structure positioned between and electrically connecting a respective one of the plurality of bumps and the first pad portion of a respective one of the plurality of pads,
wherein each of the plurality of UBM structures is offset in the first direction from the center of a respective one of the plurality of pads.
7 . The semiconductor package of claim 1 , wherein the redistribution structure further comprises a plurality of vias electrically connected to the at least one redistribution layer and extending through the at least one insulating layer, and
wherein a respective one of the plurality of vias that is closest to a respective one of the plurality of pads is located closer to the second pad portion than to the first pad portion of the respective one of the plurality of pads.
8 . The semiconductor package of claim 1 , further comprising a plurality of additional pads on a second surface of the redistribution structure,
wherein an aspect ratio of a surface of each of the plurality of additional pads is closer to 1 than an aspect ratio of a surface of each of the plurality of pads on the first surface of the redistribution structure.
9 . The semiconductor package of claim 1 , wherein an aspect ratio, which is a ratio of a length of a major axis of each of the plurality of pads to a width of the first pad portion of each of the plurality of pads, is greater than 2 and less than 5.
10 . The semiconductor package of claim 9 , wherein the length of the major axis of each of the plurality of pads is greater than 100 μm, and
wherein a width of the first pad portion of each of the plurality of pads is less than 50 μm.
11 . The semiconductor package of claim 1 , wherein the semiconductor chip is electrically connected to the redistribution structure through the plurality of bumps.
12 . The semiconductor package of claim 1 , wherein a distance between adjacent ones of the plurality of bumps is shorter than a length of a major axis of each of the plurality of pads.
13 . The semiconductor package of claim 1 , wherein each of the plurality of pads comprises a first groove in a surface of the first pad portion and a second groove in a surface of the second pad portion.
14 . A semiconductor package comprising:
a redistribution structure comprising at least one redistribution layer and at least one insulating layer alternately stacked;
a semiconductor chip electrically connected to the at least one redistribution layer; and
a plurality of bumps electrically connected to the at least one redistribution layer and arranged on one surface of the redistribution structure,
wherein the at least one redistribution layer comprises a plurality of pads arranged to face the plurality of bumps, and
wherein a surface of each of the plurality of pads that faces the plurality of bumps, has an aspect ratio greater than 2 and comprises first and second grooves.
15 . The semiconductor package of claim 14 , wherein the semiconductor chip is electrically connected to the redistribution structure through the plurality of bumps, and
wherein each of the plurality of bumps are offset in a first direction from a center of a respective one of the plurality of pads.
16 . The semiconductor package of claim 15 , wherein the redistribution structure further comprises a plurality of vias electrically connected to the at least one redistribution layer and extending through the at least one insulating layer, and
wherein a respective one of the plurality of vias that is closest to a respective one of the plurality of pads is connected to the respective one of the plurality of pads at a location offset from the center of the respective one of the plurality of pads in a second direction different from the first direction.
17 . The semiconductor package of claim 16 , wherein a distance between adjacent ones of the plurality of bumps is shorter than a length of a major axis of each of the plurality of pads.
18 . The semiconductor package of claim 17 , wherein each pad comprises,
a first pad portion offset from a center of the pad in a first direction;
a second pad portion offset from the center of the pad in a second direction; and
a connection portion connecting the first and second pad portions, wherein the connection portion comprises a protruding portion that defines a first recessed region adjacent to the first pad portion and a second recessed region adjacent to the second pad portion.
19 . A semiconductor package comprising:
a redistribution structure comprising at least one redistribution layer and at least one insulating layer alternately stacked;
a semiconductor chip electrically connected to the at least one redistribution layer; and
a plurality of bumps electrically connected to the at least one redistribution layer and arranged on one surface of the redistribution structure,
wherein the at least one redistribution layer comprises a plurality of pads arranged to face the plurality of bumps,
wherein each of the plurality of pads comprises a surface contacting a respective bump of the plurality of bumps, the surface having an aspect ratio exceeding 2, and
wherein a distance between adjacent ones of the plurality of bumps is shorter than a length of a major axis of each of the plurality of pads.
20 . The semiconductor package of claim 19 , wherein the semiconductor chip is electrically connected to the redistribution structure through the plurality of bumps,
wherein the redistribution structure further comprises a plurality of vias electrically connected to the at least one redistribution layer and extending through the at least one insulating layer,
wherein the plurality of bumps are arranged so as to be offset in a first direction from a center of each of the plurality of pads, and
wherein a respective one of the plurality of vias that is closest to a respective one of the plurality of pads is connected to the respective one of the plurality of pads at a location offset from a center of the respective one of the plurality of pads in a second direction different from the first direction.