Heterogeneous chiplet power management
The disclosed device includes heterogeneous chiplets that can communicate when each of the heterogenous chiplets has locally reached an idle state. Once receiving confirmations of the idle state from each of the heterogenous chiplets, the chiplets can complete the entry of the low power state. Various other methods, systems, and computer-readable media are also disclosed.
1 . A device comprising:
a plurality of heterogeneous chiplets, wherein a first chiplet of the plurality of heterogeneous chiplets is configured to:
report, to a second chiplet of the plurality of heterogeneous chiplets in response to receiving an indication of the device initiating entry of a low power state, locally reaching an idle state in which local clients are idle; and
in response to receiving a confirmation of the idle state from the second chiplet, locally complete the entry of the low power state.
2 . The device of claim 1 , wherein the first chiplet corresponds to a stutter client chiplet having an activity buffer and locally reaching the idle state includes filling the activity buffer based on a buffer threshold.
3 . The device of claim 2 , wherein the buffer threshold corresponds to a minimum idle period before the stutter client chiplet wakes up to refill the activity buffer.
4 . The device of claim 2 , wherein the stutter client chiplet corresponds to a display engine and the activity buffer corresponds to a display buffer.
5 . The device of claim 2 , wherein the stutter client chiplet corresponds to a multimedia engine and the activity buffer corresponds to a multimedia buffer.
6 . The device of claim 2 , wherein the stutter client chiplet is configured to receive an indication of the device transitioning to a partial power state in which a subset of logic components of the stutter client chiplet is active to allow filling the activity buffer, and wherein other chiplets of the plurality of heterogeneous chiplets remain idle.
7 . The device of claim 6 , wherein the plurality of heterogeneous chiplets are configured to abort, in response to at least one of the plurality of heterogeneous chiplets broadcasting an active state, transitioning to the partial power state while the stutter client chiplet is filling the activity buffer.
8 . The device of claim 1 , wherein locally reaching the idle state comprises at least one of saving a state, disabling write burst accumulation, or flushing remaining writes.
9 . The device of claim 1 , wherein the plurality of heterogeneous chiplets are configured to abort the entry of the low power state in response to at least one of the plurality of heterogeneous chiplets broadcasting an active state.
10 . A system comprising:
a plurality of heterogeneous chiplets including a stutter client having an activity buffer; and
a control circuit configured to:
in response to the system initiating entry of a low power state, confirm each of the plurality of heterogeneous chiplets has locally reached an idle state;
in response to receiving confirmations of the idle state from each of the plurality of heterogeneous chiplets, instruct the stutter client to fill the activity buffer to a buffer threshold; and
in response to the stutter client filling the activity buffer, complete entry of the low power state.
11 . The system of claim 10 , wherein the buffer threshold corresponds to a minimum idle period before the stutter client wakes up to refill the activity buffer.
12 . The system of claim 11 , wherein refilling the activity buffer further comprises accessing a memory of the system.
13 . The system of claim 10 , wherein the stutter client corresponds to a display engine and the activity buffer corresponds to a display buffer.
14 . The system of claim 10 , wherein the control circuit is configured to:
receive an indication of a partial power state in which only components servicing the stutter client is active; and
in response to the indication, instructing the stutter client and a corresponding link to power on, wherein other chiplets of the plurality of heterogeneous chiplets remain idle.
15 . The system of claim 14 , wherein the control circuit is configured to, in response to at least one of the plurality of heterogeneous chiplets broadcasting an active state, abort the partial power state.
16 . The system of claim 10 , wherein the control circuit is configured to abort, in response to at least one of the plurality of heterogeneous chiplets broadcasting an active state, entry of the low power state.
17 . A method comprising:
transitioning a plurality of heterogeneous chiplets to a new power state that corresponds to power gating idle chiplets of the plurality of heterogeneous chiplets;
confirming, while a stutter client chiplet of the plurality of heterogeneous chiplets is kept at least partially powered on, the idle chiplets have completed operations for reaching a fabric idle state; and
in response to confirmations from the idle chiplets of the idle state, completing the transition to the new power state.
18 . The method of claim 17 , wherein the stutter client chiplet has an activity buffer and the stutter client chiplet is kept at least partially powered on to fill the activity buffer to at least a buffer threshold.
19 . The method of claim 18 , further comprising aborting the transition to the new power state while the stutter client chiplet fills the activity buffer.
20 . The method of claim 17 , wherein the operations includes at least one of confirming corresponding local clients are idle, saving a state, flushing writes, disabling write burst accumulation, or confirming a corresponding fabric is idle.