Granted Patent B2

US 12,730,571 · App. 17/135,747 · Granted Sep 8, 2026

Inventors: Nenad Miladinovic (Campbell, CA); Hari Kannan (Sunnyvale, CA); Ronald Karr (Palo Alto, CA)

Assignee: PURE STORAGE, INC.

G06F3/0634G06F3/0619G06F3/0679G11C29/021

Abstract

Claims (50)

1 . A method, comprising:

tracking bit flips in data reads of one or more solid-state storage devices comprising flash memory in a storage system, the bit flips associated with error correction of the data reads;

comparing, by a processor that is external to the one or more solid-state storage devices, a ratio of the bit flips to a threshold value; and

adjusting a read voltage level for the flash memory in the storage system, based on the comparing.

2 . The method of claim 1 , wherein:

the tracking comprises tracking individual blocks of the flash memory; and

the adjusting the read voltage level comprises adjusting the read voltage level for a logical unit number (LUN) of the flash memory.

3 . The method of claim 1 , wherein the adjusting the read voltage comprises adjusting the read voltage for each of a plurality of read voltage levels of multilevel cell (MLC) flash memory.

4 . The method of claim 1 , wherein the adjusting the read voltage level is responsive to exceeding a threshold in the comparing.

5 . The method of claim 1 , wherein the adjusting the read voltage level comprises iteratively adjusting the read voltage level from a previous adjusted read voltage level while avoiding returning to a default read voltage level between adjustments to the read voltage level.

6 . The method of claim 1 , wherein the adjusting the read voltage level comprises communicating a command that indicates a read voltage level and an offset value for the read voltage level, to the flash memory.

7 . The method of claim 1 , wherein tracking the bit flips in the data reads of the flash memory comprises:

tracking a first set of bit flips for a first page type of the flash memory and a second set of bit flips for a second page type of the flash memory;

determining a first read voltage level for the first page type based on the tracking of the first set of bit flips and a second read voltage level for the second page type based on the tracking of the first set of bit flips; and

adjusting the read voltage level for the first page type to the first read voltage level and the read voltage level for the second page type to the second read voltage level.

8 . A non-transitory computer-readable media having instructions thereupon which, when executed by a processor, cause the processor to:

track bit flips in data reads of one or more solid-state storage devices comprising flash memory in a storage system, the bit flips associated with error correction of the data reads;

compare, by the processor that is external to the one or more solid-state storage devices, a ratio of the bit flips to a threshold value; and

adjust a read voltage level for the flash memory in the storage system, based on the comparing.

9 . The non-transitory computer-readable media of claim 8 , wherein:

the tracking is on a per block basis; and

the adjusting is on a per logical unit number (LUN) of the flash memory basis.

10 . The non-transitory computer-readable media of claim 8 , wherein the adjusting the read voltage comprises setting the read voltage for each of a plurality of read voltage levels of multilevel cell (MLC) flash memory comprising two or more bits per cell.

11 . The non-transitory computer-readable media of claim 8 , wherein a direction for the adjusting the read voltage level is responsive to a direction of the bit flips.

12 . The non-transitory computer-readable media of claim 8 , wherein the adjusting the read voltage level comprises iteratively adjusting the read voltage level from a previous read voltage level while avoiding returning to a default read voltage level between adjustments to the read voltage level.

13 . The non-transitory computer-readable media of claim 8 , wherein the adjusting the read voltage level comprises sending to the flash memory a command with an address that indicates a read voltage level and data that indicates an offset value for the read voltage level.

14 . The computer-readable media of claim 8 , wherein the processor is further configured to:

track bit flips relative to a specified page type in multilevel cell flash memory, the specified page type being upper page, lower page or extra page;

determine a value for a read voltage level that affects the bit flips relative to the specified page type; and

extrapolate at least one further value for read voltage levels of the multilevel cell flash memory based on the determined value, wherein the adjusting is based on the determining the value and the extrapolating the at least one further value.

15 . A storage system, comprising:

one or more solid-state storage devices comprising flash memory having adjustable read voltage levels; and

one or more processors that are external to the one or more solid-state storage devices, the one or more processors configured to:

track bit flips in data reads of flash memory in a storage system, the bit flips associated with error correction of the data reads;

compare a ratio of the bit flips to a threshold value; and

adjust a read voltage level for the flash memory in the storage system, based on the comparing.

16 . The storage system of claim 15 , further comprising:

a first memory, configured by the one or more processors to have a data structure that records a block identifier for each of a plurality of blocks of the flash memory, a bit flip comparison or bit flip ratio for each of the plurality of blocks, and a plurality of offsets for read voltage levels for each of the plurality of blocks.

17 . The storage system of claim 15 , wherein:

to track the bit flips is to track the bit flips of each of a plurality of blocks of the flash memory;

to compare the ratio is to form the ratio for one of the plurality of blocks of the flash memory; and

to adjust the read voltage level is to direct the read voltage level of a logical unit number (LUN) of the flash memory that includes the one of the plurality of blocks of the flash memory.

18 . The storage system of claim 15 , wherein the one or more processors and the flash memory are configured so that the read voltage level for the flash memory remains as directed, until a next read voltage level is directed, without returning to a default read voltage level.

19 . The storage system of claim 15 , wherein:

to adjust the read voltage level for the flash memory is triggered by the comparison or the ratio exceeding a threshold; and

to adjust the read voltage level for the flash memory comprises sending a command, with read voltage level selection and read voltage level value, to the flash memory.

20 . The storage system of claim 15 , wherein:

to track the bit flips and to form the comparison or the ratio is relative to a specified page type in multilevel cell flash memory;

the read voltage level is related to the bit flips and the specified page type; and

the one or more processors are further configurable to direct further read voltage levels for the flash memory based on extrapolation from the read voltage level.

Assignments (1)

Continuity (3)

References Cited (400)