Selecting an executable operation from a lookup table identified by a conditional instruction and indexed based on combined results of concurrently-computed relational operators
According to embodiments of the present disclosure, processor chips adapted for efficient massively-concurrent conditional computation are provided. In various embodiments, a chip comprises at least one processing core; a controller operatively coupled to the at least one processing core; and an instruction memory in communication with the controller. The controller is configured to: concurrently compute a plurality of relational operators on a plurality of inputs, resulting in a plurality of results; combine the plurality of results to determine an index; select an operation based on the index; and cause the at least one processing core to execute the selected operation.
1 . A chip, comprising:
at least one processing core;
a controller circuit operatively coupled to the at least one processing core; and
an instruction memory in communication with the controller circuit, the instruction memory having stored therein a program comprising a plurality of instructions, wherein the controller circuit is configured to:
select a conditional instruction from the plurality of instructions, the conditional instruction having a plurality of relational operators, wherein the plurality of relational operators comprises at least a first relational operator and a second relational operator different from the first relational operator;
concurrently compute the plurality of relational operators on a plurality of inputs, resulting in a plurality of results;
combine the plurality of results to determine an index;
select, using the index, from a lookup table, an operation, wherein the selected conditional instruction identifies the lookup table; and
cause the at least one processing core to execute the selected operation.
2 . The chip of claim 1 , wherein the controller circuit is further configured to:
select the lookup table from a plurality of lookup tables.
3 . The chip of claim 1 , wherein selecting the operation comprises:
reading the conditional instruction from the instruction memory, the conditional instruction further identifying the plurality of relational operators.
4 . The chip of claim 1 , wherein the lookup table comprises a configurable memory or register.
5 . The chip of claim 1 , wherein the plurality of relational operators are binary operators.
6 . The chip of claim 1 , wherein combining the plurality of results comprises summing.
7 . The chip of claim 1 , wherein the at least one processing core comprises a plurality of neural inference units, neural computation units, tensor computation units, matrix multipliers, vector computation units, floating point units, integer arithmetic units, and logical computation units.
8 . A method comprising:
selecting a conditional instruction from a plurality of instructions, the conditional instruction having a plurality of relational operators, wherein the plurality of relational operators comprises at least a first relational operator and a second relational operator different from the first relational operator;
concurrently computing the plurality of relational operators on a plurality of inputs, resulting in a plurality of results;
combining the plurality of results to determine an index;
selecting, using the index, from a lookup table, an operation, wherein the selected conditional instruction identifies the lookup table; and
executing, by at least one processing core, the selected operation.
9 . The method of claim 8 , further comprising:
selecting the lookup table from a plurality of lookup tables.
10 . The method of claim 8 , wherein selecting the operation comprises:
reading the conditional instruction from an instruction memory, the conditional instruction further identifying the plurality of relational operators.
11 . The method of claim 8 , wherein the plurality of relational operators are binary operators.
12 . The method of claim 8 , wherein combining the plurality of results comprises summing.
13 . The method of claim 8 , wherein the at least one processing core comprises a plurality of neural inference units, neural computation units, tensor computation units, matrix multipliers, vector computation units, floating point units, integer arithmetic units, and logical computation units.