Method for determining performance of sequential logic elements and device
A method for determining performance of sequential logic elements includes the following operations. To check a circuit, a performance check file corresponding to each of the sequential logic elements of the circuit is obtained; and the circuit is separately simulated to obtain the simulation result, by using a plurality of simulation waveforms, based on the performance check file corresponding to each of the sequential logic elements. The performance check file may be used to determine, in a simulation process, whether a target characteristic parameter of each of the sequential logic elements meets a preset condition, and identification information of a target sequential logic element having a target characteristic parameter that does not meet the preset condition is output in the simulation result.
1 . A method for determining performance of sequential logic elements of a circuit, the method comprising:
obtaining a performance check file corresponding to each of the sequential logic elements;
separately simulating the circuit based on the performance check file corresponding to each of the sequential logic elements to obtain a simulation result, by using a plurality of different simulation waveforms, wherein the plurality of different simulation waveforms comprise different clock signals and different input data signals, wherein the performance check file is used to check, in a simulation process, whether a target characteristic parameter of each of the sequential logic elements meets a preset condition, and wherein identification information of a target sequential logic element having a target characteristic parameter that does not meet the preset condition is output in the simulation result;
determining a smallest target characteristic parameter corresponding to target sequential logic elements on a same path in the simulation result and a target simulation waveform corresponding to the smallest target characteristic parameter;
determining, based on the target simulation waveform, whether a timing error exists in the target sequential logic elements on the same path; and
adjusting an input signal of the target sequential logic elements on the same path when it is determined that a timing error exists in the target sequential logic elements on the same path.
2 . The method according to claim 1 , wherein before the obtaining a performance check file corresponding to each of the sequential logic elements, the method further comprises:
generating a netlist corresponding to the circuit based on a design database of the circuit;
searching the netlist corresponding to the circuit for each of the sequential logic elements based on a preset keyword; and
configuring the performance check file corresponding to each of the sequential logic elements.
3 . The method according to claim 1 , wherein
the sequential logic elements comprise a flip-flop and/or latch; and
the target characteristic parameter comprises a setup time and/or a hold time.
4 . The method according to claim 3 , wherein the adjusting an input signal of the target sequential logic elements on the same path comprises:
adjusting a clock signal and/or a data input signal corresponding to the target sequential logic elements on the same path.
5 . An electronic device, comprising at least one processor and a memory, wherein
the memory stores computer-executable instructions; and
the at least one processor executes the computer-executable instructions stored in the memory to perform operations comprising:
obtaining a performance check file corresponding to each of sequential logic elements of a circuit;
separately simulating the circuit based on the performance check file corresponding to each of the sequential logic elements to obtain a simulation result, by using a plurality of different simulation waveforms, wherein the plurality of different simulation waveforms comprise different clock signals and different input data signals, wherein the performance check file is used to check, in a simulation process, whether a target characteristic parameter of each of the sequential logic elements meets a preset condition, and wherein identification information of a target sequential logic element having a target characteristic parameter that does not meet the preset condition is output in the simulation result;
determining a smallest target characteristic parameter corresponding to target sequential logic elements on a same path in the simulation result and a target simulation waveform corresponding to the smallest target characteristic parameter;
determining, based on the target simulation waveform, whether a timing error exists in the target sequential logic elements on the same path; and
adjusting an input signal of the target sequential logic elements on the same path when it is determined that a timing error exists in the target sequential logic elements on the same path.
6 . The electronic device according to claim 5 , wherein before the obtaining a performance check file corresponding to each of the sequential logic elements, the operations further comprise:
generating a netlist corresponding to the circuit based on a design database of the circuit;
searching the netlist corresponding to the circuit for each of the sequential logic elements based on a preset keyword; and
configuring the performance check file corresponding to each of the sequential logic elements.
7 . The electronic device according to claim 5 , wherein
the sequential logic elements comprise a flip-flop and/or latch; and
the target characteristic parameter comprises a setup time and/or a hold time.
8 . The electronic device according to claim 7 , wherein the adjusting an input signal of the target sequential logic elements on the same path comprises:
adjusting a clock signal and/or a data input signal corresponding to the target sequential logic elements on the same path.
9 . A non-transitory computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and when a processor executes the computer-executable instructions, the computer-executable instructions cause the processor to perform operations comprising:
obtaining a performance check file corresponding to each of sequential logic elements of a circuit;
separately simulating the circuit based on the performance check file corresponding to each of the sequential logic elements to obtain a simulation result, by using a plurality of different simulation waveforms, wherein the plurality of different simulation waveforms comprise different clock signals and different input data signals, wherein the performance check file is used to check, in a simulation process, whether a target characteristic parameter of each of the sequential logic elements meets a preset condition, and wherein identification information of a target sequential logic element having a target characteristic parameter that does not meet the preset condition is output in the simulation result;
determining a smallest target characteristic parameter corresponding to target sequential logic elements on a same path in the simulation result and a target simulation waveform corresponding to the smallest target characteristic parameter;
determining, based on the target simulation waveform, whether a timing error exists in the target sequential logic elements on the same path; and
adjusting an input signal of the target sequential logic elements on the same path when it is determined that a timing error exists in the target sequential logic elements on the same path.
10 . The non-transitory computer-readable storage medium according to claim 9 , wherein before the obtaining a performance check file corresponding to each of the sequential logic elements, the operations further comprise:
generating a netlist corresponding to the circuit based on a design database of the circuit;
searching the netlist corresponding to the circuit for each of the sequential logic elements based on a preset keyword; and
configuring the performance check file corresponding to each of the sequential logic elements.
11 . The non-transitory computer-readable storage medium according to claim 9 , wherein
the sequential logic elements comprise a flip-flop and/or latch; and
the target characteristic parameter comprises a setup time and/or a hold time.
12 . The non-transitory computer-readable storage medium according to claim 11 , wherein the adjusting an input signal of the target sequential logic elements on the same path comprises:
adjusting a clock signal and/or a data input signal corresponding to the target sequential logic elements on the same path.