Granted Patent B2

US 12,731,520 · App. 18/389,600 · Granted Sep 8, 2026

Inventors: Peter F Holland (Los Gatos, CA); Christopher P Tann (San Jose, CA); Ramana V Rachakonda (Austin, TX)

Assignee: Apple Inc.

G09G3/2092G09G2310/08G09G2330/023

Abstract

Claims (66)

1 . An electronic device, comprising:

first circuitry configured to present, based on a timing signal, an image;

second circuitry;

a first timing generator coupled to the first circuitry and the second circuitry, wherein the first timing generator is configured to generate the timing signal for the first circuitry while the second circuitry is operated in a lower-power mode; and

a second timing generator coupled to the first circuitry, the second circuitry, and the first timing generator, wherein the second timing generator is configured to generate the timing signal for the first circuitry while the second circuitry is operated in a higher-power mode, wherein the first timing generator is configured to:

generate a synchronization signal to control whether the second timing generator is operated to generate the timing signal;

transmit the synchronization signal to the second timing generator;

receive a first timing signal from the second timing generator;

generate a second timing signal; and

transmit a control signal to cause routing circuitry to transmit the first timing signal based on the first timing signal being synchronized to the second timing signal.

2 . The electronic device of claim 1 , wherein the second circuitry comprises image processing circuitry.

3 . The electronic device of claim 2 , wherein the image processing circuitry is part of a system-on-chip that comprises the first timing generator and the second timing generator.

4 . The electronic device of claim 3 , wherein the first circuitry is not part of the system-on-chip.

5 . The electronic device of claim 1 , wherein the first timing generator, the second timing generator, and the second circuitry are part of a system-on-chip, and wherein the first circuitry is not part of the system-on-chip.

6 . The electronic device of claim 5 , wherein the first circuitry comprises electronic display circuitry and the second circuitry comprises image processing circuitry configured to process image data before the image data is displayed by the electronic display circuitry.

7 . The electronic device of claim 6 , comprising:

a first power domain electrically coupled to power the second circuitry and the second timing generator; and

a second power domain electrically coupled to power the first timing generator.

8 . The electronic device of claim 1 , wherein the first circuitry comprises control circuitry configured to perform one or more operations of the following operations based on the timing signal:

aligning generation operations to the timing signal;

setting image frame presentation durations;

aligning an emissivity loop;

triggering touch scan operations; or

controlling an arbitrary presentation time display mode; or

any combination thereof.

9 . The electronic device of claim 1 , comprises a configuration register, wherein the first timing generator is configured to generate the timing signal at least in part by:

reading a first indication of a first number of clocking signal edges in each video line from the configuration register, and generating the timing signal based on comparing a first count of received edges of a clocking signal to the first number; or

reading a second indication of a second number of video lines in each image frame from the configuration register, and generating the timing signal based on comparing a second count of received video lines to the second number; or

both.

10 . The electronic device of claim 1 , wherein the second timing generator is configured to:

receive the synchronization signal from the first timing generator; and

generate the first timing signal based on the synchronization signal and a configuration parameter, wherein the second timing generator is configured to generate the first timing signal at an at least partially overlapping time duration as the first timing generator generates the second timing signal.

11 . An electronic device, comprising:

first circuitry;

second circuitry;

a first timing generator coupled to the first circuitry and the second circuitry, wherein the first timing generator is configured to generate a plurality of timing signals for the first circuitry while the second circuitry is operated in a lower-power mode, and wherein the first timing generator comprises a plurality of multiplexer circuitry configured to transmit the plurality of timing signals; and

a second timing generator coupled to the plurality of multiplexer circuitry, wherein the second timing generator is configured to generate the plurality of timing signals for the first circuitry while the second circuitry is operated in a higher-power mode.

12 . The electronic device of claim 11 , wherein the first circuitry comprises control circuitry configured to perform one or more operations of the following operations based on a timing signal:

aligning generation operations to the timing signal;

setting image frame presentation durations;

aligning an emissivity loop;

triggering touch scan operations; or

controlling an arbitrary presentation time display mode; or

any combination thereof.

13 . The electronic device of claim 11 , wherein the first circuitry comprises electronic display circuitry, and wherein the second circuitry comprises image processing circuitry.

14 . The electronic device of claim 11 , wherein the second circuitry is part of a system-on-chip that comprises the first timing generator and the second timing generator.

15 . The electronic device of claim 14 , wherein the first circuitry is not part of the system-on-chip.

16 . The electronic device of claim 11 , wherein the first timing generator is configured to synchronize with the second timing generator in association with the second circuitry being operated in the higher-power mode.

17 . An electronic device, comprising:

first circuitry;

second circuitry;

a configuration register configured to store a first indication of a first number of clocking signal edges in each video line, a second indication of a second number of video lines in each image frame, or both;

a first timing generator coupled to the first circuitry and the second circuitry, wherein the first timing generator is configured to generate a timing signal for the first circuitry while the second circuitry is operated in a lower-power mode at least in part by:

reading the first indication from the configuration register, and generating the timing signal based on comparing a first count of received edges of a clocking signal to the first number; or

reading the second indication from the configuration register, and generating the timing signal based on comparing a second count of received video lines to the second number; or

both; and

a second timing generator coupled to the first circuitry, the second circuitry, and the first timing generator, wherein the second timing generator is configured to generate the timing signal for the first circuitry while the second circuitry is operated in a higher-power mode.

18 . The electronic device of claim 17 , wherein the first timing generator is configured to synchronize with the second timing generator in association with the second circuitry being operated in the higher-power mode.

19 . The electronic device of claim 17 , wherein the first timing generator, the second timing generator, and the second circuitry are part of a system-on-chip, and wherein the first circuitry is not part of the system-on-chip.

20 . The electronic device of claim 17 , wherein the first circuitry comprises control circuitry configured to perform one or more operations of the following operations based on the timing signal:

aligning generation operations to the timing signal;

setting image frame presentation durations;

aligning an emissivity loop;

triggering touch scan operations; or

controlling an arbitrary presentation time display mode; or

any combination thereof.

Continuity (3)

References Cited (23)