Gate driver and display device including the same
A gate driver including: first to N-th stages receiving first to N-th clock signals from first to N-th clock lines, the first stage includes a first clock terminal receiving the first clock signal, a second clock terminal receiving a second clock signal, a carry terminal receiving a vertical start signal, and an output terminal outputting a first gate signal, an N−K-th stage includes a first clock terminal receiving an N−K-th clock signal, a second clock terminal receiving an N−K+1-th clock signal, a carry terminal receiving an N−K−1-th gate signal, and an output terminal outputting an N−K-th gate signal, and the N-th stage includes a first clock terminal receiving the N-th clock signal, a second clock terminal receiving the first clock signal, a carry terminal receiving an N−1-th gate signal, and an output terminal outputting an N-th gate signal.
1 . A gate driver comprising:
first to N-th stages (where N is a positive integer of 3 or more) for receiving first to N-th clock signals from first to N-th clock lines,
wherein the first stage includes a first clock terminal for receiving the first clock signal, a second clock terminal for receiving a second clock signal, a carry terminal for receiving a vertical start signal, and an output terminal for outputting a first gate signal,
wherein an N−K-th stage (where K is a positive integer between 1 and N−2) includes a first clock terminal for receiving an N−K-th clock signal, a second clock terminal for receiving an N−K+1-th clock signal, a carry terminal for receiving an N−K−1-th gate signal, and an output terminal for outputting an N−K-th gate signal,
wherein the N-th stage includes a first clock terminal for receiving the N-th clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving an N−1-th gate signal, and an output terminal for outputting an N-th gate signal,
wherein the first stage further includes:
a first transistor including a gate electrode for receiving the first clock signal, a first electrode for receiving the vertical start signal, and a second electrode connected to a first control node;
a second transistor including a gate electrode connected to an inverting control node, a first electrode for receiving a high gate voltage, and a second electrode;
a third transistor including a gate electrode for receiving the second clock signal, a first electrode connected to the second electrode of the second transistor, and a second electrode connected to the first control node;
a fourth transistor including a gate electrode connected to the first control node, a first electrode for receiving the first clock signal, and a second electrode connected to the inverting control node;
a fifth transistor including a gate electrode for receiving the first clock signal, a first electrode for receiving a low gate voltage, and a second electrode connected to the inverting control node;
a sixth transistor including a gate electrode connected to the inverting control node, a first electrode for receiving the high gate voltage, and a second electrode connected to a gate output node configured to output the first gate signal;
a seventh transistor including a gate electrode connected to a second control node, a first electrode for receiving the second clock signal, and a second electrode connected to the gate output node;
a first capacitor including a first electrode for receiving the high gate voltage and a second electrode connected to the inverting control node; and
a second capacitor including a first electrode connected to the second control node and a second electrode connected to the gate output node, and
wherein an activation period of each of the first to N-th clock signals does not overlap with each other.
2 . The gate driver of claim 1 , wherein, when N is 4, the gate driver comprises:
the first stage;
a second stage including a first clock terminal for receiving the second clock signal, a second clock terminal for receiving a third clock signal, a carry terminal for receiving the first gate signal, and an output terminal for outputting a second gate signal;
a third stage including a first clock terminal for receiving the third clock signal, a second clock terminal for receiving a fourth clock signal, a carry terminal for receiving the second gate signal, and an output terminal for outputting a third gate signal; and
a fourth stage including a first clock terminal for receiving the fourth clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving the third gate signal, and an output terminal for outputting a fourth gate signal.
3 . The gate driver of claim 1 , when N is 6, the gate driver comprises:
the first stage;
a second stage including a first clock terminal for receiving the second clock signal, a second clock terminal for receiving a third clock signal, a carry terminal for receiving the first gate signal, and an output terminal for outputting a second gate signal;
a third stage including a first clock terminal for receiving the third clock signal, a second clock terminal for receiving a fourth clock signal, a carry terminal for receiving the second gate signal, and an output terminal for outputting a third gate signal;
a fourth stage including a first clock terminal for receiving the fourth clock signal, a second clock terminal for receiving a fifth clock signal, a carry terminal for receiving the third gate signal, and an output terminal for outputting a fourth gate signal;
a fifth stage including a first clock terminal for receiving the fifth clock signal, a second clock terminal for receiving a sixth clock signal, a carry terminal for receiving the fourth gate signal, and an output terminal for outputting a fifth gate signal; and
a sixth stage including a first clock terminal for receiving the sixth clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving the fifth gate signal, and an output terminal for outputting a sixth gate signal.
4 . The gate driver of claim 1 , wherein, when a length of the activation period of each of the first to N-th clock signals is J horizontal time (where J is a positive number), a length of a deactivation period of each of the first to N-th clock signals is (N−1)×J horizontal time and a period of each of the first to N-th clock signals is N×J horizontal time.
5 . The gate driver of claim 4 , wherein, when N is 4 and J is 1, the length of the activation period of each of the first to N-th clock signals is 1 horizontal time and the length of the deactivation period of each of the first to N-th clock signals is 3 horizontal times, and a period of each of the first to N-th clock signals is 4 horizontal times.
6 . The gate driver of claim 4 , wherein, when N increases, the period of each of the first to N-th clock signals increases.
7 . The gate driver of claim 4 , wherein, when N increases, a capacitance of an equivalent capacitor viewed from each of the first to N-th clock lines decreases.
8 . The gate driver of claim 1 , the first stage further includes:
an eighth transistor including a gate terminal for receiving the low gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.
9 . A display device comprising:
a display panel including pixels; and
a gate driver configured to provide gate signals to the display panel,
wherein the gate driver includes first to N-th stages (where N is a positive integer of 3 or more) for receiving first to N-th clock signals from first to N-th clock lines,
wherein the first stage includes a first clock terminal for receiving the first clock signal, a second clock terminal for receiving a second clock signal, a carry terminal for receiving a vertical start signal, and an output terminal for outputting a first gate signal,
wherein an N−K-th stage (where K is a positive integer between 1 and N−2) includes a first clock terminal for receiving an N−K-th clock signal, a second clock terminal for receiving an N−K+1-th clock signal, a carry terminal for receiving an N−K−1-th gate signal, and an output terminal for outputting an N−K-th gate signal,
wherein the N-th stage includes a first clock terminal for receiving the N-th clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving an N−1-th gate signal, and an output terminal for outputting an N-th gate signal,
wherein the first stage further includes:
a first transistor including a gate electrode for receiving the first clock signal, a first electrode for receiving the vertical start signal, and a second electrode connected to a first control node;
a second transistor including a gate electrode connected to an inverting control node, a first electrode for receiving a high gate voltage, and a second electrode;
a third transistor including a gate electrode for receiving the second clock signal, a first electrode connected to the second electrode of the second transistor, and a second electrode connected to the first control node;
a fourth transistor including a gate electrode connected to the first control node, a first electrode for receiving the first clock signal, and a second electrode connected to the inverting control node;
a fifth transistor including a gate electrode for receiving the first clock signal, a first electrode for receiving a low gate voltage, and a second electrode connected to the inverting control node;
a sixth transistor including a gate electrode connected to the inverting control node, a first electrode for receiving the high gate voltage, and a second electrode connected to a gate output node configured to output the first gate signal;
a seventh transistor including a gate electrode connected to a second control node, a first electrode for receiving the second clock signal, and a second electrode connected to the gate output node;
a first capacitor including a first electrode for receiving the high gate voltage and a second electrode connected to the inverting control node; and
a second capacitor including a first electrode connected to the second control node and a second electrode connected to the gate output node, and
wherein an activation period of each of the first to N-th clock signals does not overlap with each other.
10 . The display device of claim 9 , wherein, when N is 4, the gate driver comprises:
the first stage including the first clock terminal for receiving the first clock signal, a second clock terminal for receiving the second clock signal, the carry terminal for receiving the vertical start signal, and the output terminal for outputting the first gate signal;
a second stage including a first clock terminal for receiving the second clock signal, a second clock terminal for receiving a third clock signal, a carry terminal for receiving the first gate signal, and an output terminal for outputting a second gate signal;
a third stage including a first clock terminal for receiving the third clock signal, a second clock terminal for receiving a fourth clock signal, a carry terminal for receiving the second gate signal, and an output terminal for outputting a third gate signal; and
a fourth stage including a first clock terminal for receiving the fourth clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving the third gate signal, and an output terminal for outputting a fourth gate signal.
11 . An electronic device comprising:
a display device comprising:
a display panel including pixels; and
a gate driver configured to provide gate signals to the display panel, wherein the gate driver includes first to N-th stages (where N is a positive integer of 3 or more) for receiving first to N-th clock signals from first to N-th clock lines,
wherein the first stage includes a first clock terminal for receiving the first clock signal, a second clock terminal for receiving a second clock signal, a carry terminal for receiving a vertical start signal, and an output terminal for outputting a first gate signal,
wherein an N−K-th stage (where K is a positive integer between 1 and N−2) includes a first clock terminal for receiving an N−K-th clock signal, a second clock terminal for receiving an N−K+1-th clock signal, a carry terminal for receiving an N−K−1-th gate signal, and an output terminal for outputting an N−K-th gate signal,
wherein the N-th stage includes a first clock terminal for receiving the N-th clock signal, a second clock terminal for receiving the first clock signal, a carry terminal for receiving an N−1-th gate signal, and an output terminal for outputting an N-th gate signal,
wherein the first stage includes:
a first transistor including a gate electrode for receiving the first clock signal, a first electrode for receiving the vertical start signal, and a second electrode connected to a first control node;
a second transistor including a gate electrode connected to an inverting control node, a first electrode for receiving a high gate voltage, and a second electrode;
a third transistor including a gate electrode for receiving the second clock signal, a first electrode connected to the second electrode of the second transistor, and a second electrode connected to the first control node;
a fourth transistor including a gate electrode connected to the first control node, a first electrode for receiving the first clock signal, and a second electrode connected to the inverting control node;
a fifth transistor including a gate electrode for receiving the first clock signal, a first electrode for receiving a low gate voltage, and a second electrode connected to the inverting control node;
a sixth transistor including a gate electrode connected to the inverting control node, a first electrode for receiving the high gate voltage, and a second electrode connected to a gate output node configured to output the first gate signal;
a seventh transistor including a gate electrode connected to a second control node, a first electrode for receiving the second clock signal, and a second electrode connected to the gate output node;
a first capacitor including a first electrode for receiving the high gate voltage and a second electrode connected to the inverting control node; and
a second capacitor including a first electrode connected to the second control node and a second electrode connected to the gate output node, and
wherein an activation period of each of the first to N-th clock signals does not overlap with each other.
12 . The electronic device of claim 11 , wherein the first stage further includes:
an eighth transistor including a gate terminal for receiving the low gate voltage, a first electrode connected to the first control node, and a second electrode connected to the second control node.