Dual mode clock and data recovery circuit using oversampling or baud rate and method of operating same
Disclosed are a clock and data recovery circuit and a method of operating the same. The clock and data recovery circuit includes an analog front end that receives an external signal and outputs a non-zero return (NRZ) signal, a comparison unit that receives the NRZ signal and compares the NRZ signal with a reference voltage to generate a phase of the external signal and data; a phase detector that determines a transmission rate of the data based on the phase and generates a first recovery signal and a second recovery signal based on the transmission rate of the data; and an oscillator that generates a first clock in an oversampling scheme based on the first recovery signal and generates a second clock in a baud rate scheme based on the second recovery signal.
1 . A clock and data recovery circuit comprising:
an analog front end configured to receive an external signal and output a non-zero return (NRZ) signal;
a phase comparator configured to receive the NRZ signal and compare the NRZ signal with a reference voltage to generate a phase of the external signal and data;
a phase detector configured to determine a transmission rate of the data based on the phase and generate a first recovery signal and a second recovery signal based on the transmission rate of the data; and
an oscillator configured to generate a first clock in an oversampling scheme based on the first recovery signal and generate a second clock in a baud rate scheme based on the second recovery signal.
2 . The clock and data recovery circuit of claim 1 , wherein the phase detector is configured to:
generate the first recovery signal when the transmission rate of the data is equal to or less than a determination reference; and
generate the second recovery signal when the transmission rate of the data exceeds the determination reference.
3 . The clock and data recovery circuit of claim 2 , wherein the phase comparator is configured to perform sampling at CK0 and CK180 timings according to the first clock generated based on the first recovery signal,
wherein the CK0 timing is a timing at a 0-degree phase of the first clock and the CK180 timing is a timing at a 180-degree phase of the first clock.
4 . The clock and data recovery circuit of claim 2 , wherein the phase comparator is configured to perform sampling at CK0 timing according to the second clock generated based on the second recovery signal,
wherein the CK0 timing is a timing at a 0-degree phase of the second clock.
5 . The clock and data recovery circuit of claim 1 , further comprising:
an adaptation circuitry configured to apply a least mean square algorithm to the analog front end.
6 . A method of operating a clock and data recovery circuit, the method comprising:
receiving an external signal and outputting a non-zero return (NRZ) signal;
receiving the NRZ signal and comparing the NRZ signal with a reference voltage to generate a phase of the external signal and data;
determining a transmission rate of the data based on the phase and generating a first recovery signal and a second recovery signal based on the transmission rate of the data; and
generating a first clock in an oversampling scheme based on the first recovery signal and generating a second clock in a baud rate scheme based on the second recovery signal.
7 . The method of claim 6 , wherein the generating of the first recovery signal and the second recovery signal includes:
generating the first recovery signal when the transmission rate of the data is equal to or less than a determination reference; and
generating the second recovery signal when the transmission rate of the data exceeds the determination reference.
8 . The method of claim 7 , wherein the generating of the phase and the data includes performing sampling at CK0 and CK180 timings according to the first clock generated based on the first recovery signal,
wherein the CK0 timing is a timing at a 0-degree phase of the first clock and the CK180 timing is a timing at a 180-degree phase of the first clock.
9 . The method of claim 7 , wherein the generating of the phase and the data includes performing sampling at CK0 timing according to the second clock generated based on the second recovery signal,
wherein the CK0 timing is a timing at a 0-degree phase of the second clock.
10 . The method of claim 6 , further comprising:
applying a least mean square algorithm to an analog front end of the clock and data recovery circuit.