DC balanced transition encoding
A system and method for DC balanced transition encoding. In some embodiments, the method includes: generating a set of candidate encoding keys for a set of raw data words; selecting a first encoding key, of the set of candidate encoding keys, based on a first disparity contribution; and encoding the raw data words with the first encoding key, the first disparity contribution being a difference between the number of ones and the number of zeros in the result of encoding the set of raw data words with the first encoding key.
1 . A method, comprising:
generating a set of candidate encoding keys for a set of raw data words;
encoding the set of the raw data words using the set of candidate encoding keys to generate encoded packets;
determining a disparity for each of the encoded packets;
selecting an encoded packet, from among the encoded packets with a minimum disparity from among the disparity for each of the encoded packets; and
transmitting the encoded packet to a driver.
2 . The method of claim 1 , wherein the disparity for each packet is a difference between a number of ones and a number of zeroes in each of the encoded packets.
3 . The method of claim 1 , wherein the determining the disparity for each of the encoded packets comprises:
calculating a set of bit level disparities, each corresponding to a bit level of the raw data words;
changing a sign of each bit level disparity corresponding to a one in a corresponding encoding key from among the set of candidate encoding keys, to form a set of polarity-adjusted bit level disparities; and
summing:
the polarity-adjusted bit level disparities; and
a disparity of a corresponding encoding key,
wherein:
an absolute value of the bit level disparity at each bit level is equal to the absolute value of a difference between
a number of ones, at the bit level, in all of the raw data words, and
a number of zeros at the bit level, in all of the raw data words; and
an absolute value of the disparity of the corresponding encoding key is equal to an absolute value of a difference between a number of ones of the corresponding encoding key and a number of zeros of the corresponding encoding key.
4 . The method of claim 3 , wherein the calculating a bit level disparity, of the set of bit level disparities, at a first bit level, comprises calculating a difference between
twice the number of ones at the first bit level and
the number of raw data words.
5 . The method of claim 1 , wherein a result of the encoding the set of the raw data words with a corresponding encoding key comprises:
the corresponding encoding key; and
an exclusive-OR of the corresponding encoding key with each of the raw data words.
6 . The method of claim 1 , wherein a result of the encoding the set of the raw data words with a corresponding encoding key is a set of encoded data words having a maximum run length not exceeding a first threshold.
7 . The method of claim 6 , wherein the result of the encoding the set of the raw data words with the corresponding encoding key comprises:
the corresponding encoding key; and
an exclusive-OR of the corresponding encoding key with each of the raw data words.
8 . A system, comprising:
a processing circuit; and
a memory connected to the processing circuit, the memory storing instructions that, when executed by the processing circuit, cause the system to perform a method, the method comprising:
generating a set of candidate encoding keys for a set of raw data words;
encoding the set of the raw data words using the set of candidate encoding keys to generate encoded packets;
determining a disparity for each of the encoded packets;
selecting an encoded packet, from among the encoded packets with a minimum disparity from among the disparity for each of the encoded packets; and
transmitting the encoded packet to a driver.
9 . The system of claim 8 , wherein the disparity for each packet is a difference between a number of ones and a number of zeroes in each of the encoded packets.
10 . The system of claim 8 , wherein the determining the disparity for each of the encoded packets comprises:
calculating a set of bit level disparities, each corresponding to a bit level of the raw data words;
changing a sign of each bit level disparity corresponding to a one in a corresponding encoding key from among the set of candidate encoding keys, to form a set of polarity-adjusted bit level disparities; and
summing:
the polarity-adjusted bit level disparities; and
a disparity of a corresponding encoding key,
wherein:
an absolute value of the bit level disparity at each bit level is equal to the absolute value of a difference between
a number of ones, at the bit level, in all of the raw data words, and
a number of zeros at the bit level, in all of the raw data words; and
an absolute value of the disparity of the corresponding encoding key is equal to an absolute value of a difference between a number of ones of the corresponding encoding key and a number of zeros of the corresponding encoding key.
11 . The system of claim 10 , wherein the calculating a bit level disparity, of the set of bit level disparities, at a first bit level, comprises calculating a difference between
twice the number of ones at the first bit level and
the number of raw data words.
12 . The system of claim 8 , wherein a result of the encoding the set of the raw data words with a corresponding encoding key comprises:
the corresponding encoding key; and
an exclusive-OR of the corresponding encoding key with each of the raw data words.
13 . The system of claim 8 , wherein a result of the encoding the set of the raw data words with a corresponding encoding key is a set of encoded data words having a maximum run length not exceeding a first threshold.
14 . The system of claim 13 , wherein the result of the encoding the set of the raw data words with the corresponding encoding key comprises:
the corresponding encoding key; and
an exclusive-OR of the corresponding encoding key with each of the raw data words.
15 . A display, comprising:
a timing controller; and
a driver integrated circuit,
the timing controller comprising:
a processing circuit; and
a memory connected to the processing circuit, the memory storing instructions that, when executed by the processing circuit, cause the timing controller to perform a method, the method comprising:
generating a set of candidate encoding keys for a set of raw data words;
encoding the set of the raw data words using the set of candidate encoding keys to generate encoded packets;
determining a disparity for each of the encoded packets;
selecting an encoded packet, from among the encoded packets with a minimum disparity from among the disparity for each of the encoded packets; and
transmitting the encoded packet to the driver integrated circuit.
16 . The display of claim 15 , wherein the disparity for each packet is a difference between a number of ones and a number of zeroes in each of the encoded packets.
17 . The display of claim 15 , wherein the determining the disparity for each of the encoded packets comprises:
calculating a set of bit level disparities, each corresponding to a bit level of the raw data words;
changing a sign of each bit level disparity corresponding to a one in a corresponding encoding key from among the set of candidate encoding keys, to form a set of polarity-adjusted bit level disparities; and
summing:
the polarity-adjusted bit level disparities; and
a disparity of a corresponding encoding key,
wherein:
an absolute value of the bit level disparity at each bit level is equal to the absolute value of a difference between
a number of ones, at the bit level, in all of the raw data words, and
a number of zeros at the bit level, in all of the raw data words; and
an absolute value of the disparity of the corresponding encoding key is equal to an absolute value of a difference between a number of ones of the corresponding encoding key and a number of zeros of the corresponding encoding key.
18 . The display of claim 17 , wherein the calculating a bit level disparity, of the set of bit level disparities, at a first bit level, comprises calculating a difference between
twice the number of ones at the first bit level and
the number of raw data words.
19 . The display of claim 15 , wherein a result of the encoding the set of the raw data words with a corresponding encoding key comprises:
the corresponding encoding key; and
an exclusive-OR of the corresponding encoding key with each of the raw data words.
20 . The display of claim 15 , wherein a result of the encoding the set of the raw data words with a corresponding encoding key is a set of encoded data words having a maximum run length not exceeding a threshold.