Semiconductor memory device and method of manufacturing the same
A semiconductor memory device according to an embodiment includes: a substrate; a bit line positioned on the substrate and extending in a first direction; a channel accommodating insulating layer positioned on the substrate, and defining a channel trench exposing the bit line and extending in a second direction crossing the first direction; a channel layer extending along a bottom surface and a side surface of the channel trench and contacting the bit line; a word line positioned in the channel trench and extending in the second direction; a gate insulating layer positioned between the channel layer and the word line; and a capacitor structure positioned on the channel layer and electrically connected to the channel layer, in which the channel layer has a double layer structure of an oxide semiconductor layer and a first graphene layer.
1 . A semiconductor memory device, comprising:
a substrate;
a bit line on the substrate and extending in a first direction;
a channel accommodating insulating layer positioned on the substrate, and defining a channel trench extending in a second direction crossing the first direction;
a channel layer extending along a bottom surface and a side surface of the channel trench and contacting the bit line;
a word line in the channel trench and extending in the second direction;
a gate insulating layer separating the channel layer from the word line; and
a capacitor structure on the channel layer and electrically connected to the channel layer,
wherein the channel layer has a double layer structure of an oxide semiconductor layer and a first graphene layer, and
wherein, in a stacking direction perpendicular to the first direction, a portion of the first graphene layer is stacked on a portion of the oxide semiconductor layer which is stacked on a portion of the bit line.
2 . The semiconductor memory device of claim 1 , wherein:
the channel layer further includes a second graphene layer, and
the oxide semiconductor layer is interposed between the first graphene layer and the second graphene layer.
3 . The semiconductor memory device of claim 2 , wherein:
the oxide semiconductor layer includes amorphous indium gallium zinc oxide (IGZO).
4 . The semiconductor memory device of claim 2 , wherein:
a thickness of each of the first and second graphene layers is about 0.3 nm to about 2 nm.
5 . The semiconductor memory device of claim 1 , wherein:
a first surface of the oxide semiconductor layer is in electrical contact with the bit line, and
a second surface opposite to the first surface of the oxide semiconductor layer is in electrical contact with the first graphene layer.
6 . The semiconductor memory device of claim 5 , wherein:
the oxide semiconductor layer includes amorphous indium gallium zinc oxide (IGZO).
7 . The semiconductor memory device of claim 5 , wherein:
a thickness of the first graphene layer is about 0.3 nm to about 2 nm.
8 . A semiconductor memory device, comprising:
a substrate;
a bit line on the substrate and extending in a first direction;
a word line on the substrate, electrically insulated from the bit line, and extending in a second direction crossing the first direction;
a channel layer on the substrate, in electrical contact with the bit line, and insulated from the word line; and
a capacitor structure electrically connected to the channel layer,
wherein the channel layer includes:
an oxide semiconductor layer in electrical contact with the bit line; and
a first graphene layer on the oxide semiconductor layer, and
wherein, in a stacking direction perpendicular to the first direction, a portion of the first graphene layer is stacked on a portion of the oxide semiconductor layer which is stacked on a portion of the bit line.
9 . The semiconductor memory device of claim 8 , wherein:
the channel layer further includes a second graphene layer, and
the oxide semiconductor layer is interposed between the first graphene layer and the second graphene layer.
10 . The semiconductor memory device of claim 9 , wherein:
the oxide semiconductor layer includes amorphous indium gallium zinc oxide (IGZO).
11 . The semiconductor memory device of claim 9 , wherein:
a thickness of each of the first and second graphene layers is about 0.3 nm to about 2 nm.
12 . The semiconductor memory device of claim 8 , wherein:
the oxide semiconductor layer includes amorphous indium gallium zinc oxide (IGZO).
13 . The semiconductor memory device of claim 8 , wherein:
a thickness of the first graphene layer is about 0.3 nm to about 2 nm.
14 . A method of manufacturing a semiconductor memory device, the method comprising:
forming a bit line extending in a first direction on a substrate;
forming a channel accommodating insulating layer on the substrate to define a channel trench, wherein the channel trench exposes at least a portion of the bit line and extending in a second direction crossing the first direction;
stacking an oxide semiconductor layer on the substrate and the channel accommodating insulating layer;
stacking a first graphene layer on the oxide semiconductor layer;
forming a photoresist film on the first graphene layer;
forming a channel layer by etching the first graphene layer and the oxide semiconductor layer by using the photoresist film as a mask;
exposing the first graphene layer of the channel layer by removing the photoresist film;
forming a word line extending in the second direction;
forming a gate insulating layer positioned between the channel layer and the word line; and
forming a capacitor structure positioned on the channel layer and electrically connected to the channel layer,
wherein, in a stacking direction perpendicular to the first direction, a portion of the first graphene layer is stacked on a portion of the oxide semiconductor layer which is stacked on a portion of the bit line.
15 . The method of claim 14 , further comprising:
stacking a second graphene layer on the substrate and the channel accommodating insulating layer, wherein the oxide semiconductor layer is stacked on the second graphene layer,
wherein the forming of the channel layer further includes etching the second graphene layer, and
wherein the second graphene layer is in contact with the bit line.
16 . The method of claim 15 , wherein:
the oxide semiconductor layer includes amorphous indium gallium zinc oxide (IGZO).
17 . The method of claim 15 , wherein:
a thickness of each of the first and second graphene layers is about 0.3 nm to about 2 nm.
18 . The method of claim 14 , wherein:
a first surface of the oxide semiconductor layer is in physical contact with the bit line, and
a second surface opposite to the first surface of the oxide semiconductor layer is in physical contact with the first graphene layer.
19 . The method of claim 14 , wherein:
the oxide semiconductor layer includes amorphous indium gallium zinc oxide (IGZO).
20 . The method of claim 14 , wherein:
a thickness of the first graphene layer is about 0.3 nm to about 2 nm.