Semiconductor memory device and method of manufacturing semiconductor memory device
A semiconductor memory device includes: a stack having conductive layers and insulating layers, the conductive layers including a first select gate line connected to a gate of a first select transistor, a word line provided above the first select gate line and connected to a gate of a memory transistor, and a second select gate line provided above the word line and connected to a gate of a second select transistor; a core insulating layer having a top surface lower than a top surface of the second select gate line; a semiconductor layer having a first semiconductor part having channel formation regions of the transistors and a second semiconductor part on the top surface of the core insulating layer; and a memory layer between the semiconductor layer and the stack. The first semiconductor part has an impurity semiconductor region containing an impurity and overlapping with the second select gate line.
1 . A semiconductor memory device comprising:
a peripheral circuit provided on a surface of a semiconductor substrate; and
a memory cell array provided above the peripheral circuit, wherein
the memory cell array includes:
a stack having conductive layers and insulating layers, each conductive layer and each insulating layer being alternately stacked and extending in a first direction,
the conductive layers including
a first select gate line connected to a gate of a first select transistor,
a word line provided above the first select gate line and connected to a gate of a memory transistor, and
a second select gate line provided above the word line and connected to a gate of a second select transistor,
a core insulating layer extending in a second direction intersecting the first direction, the core insulating layer having a top surface lower than a top surface of the second select gate line with respect to the surface of the semiconductor substrate;
a semiconductor layer extending in the second direction, the semiconductor layer having a first semiconductor part and a second semiconductor part, the first semiconductor part having channel formation regions of the memory transistor and the first and second select transistors, and the second semiconductor part being provided on the top surface of the core insulating layer; and
a memory layer provided between the semiconductor layer and the stack in the first direction, wherein
the first semiconductor part has an impurity semiconductor region containing an impurity element and overlapping with the second select gate line, and
the semiconductor memory device further comprises:
a cap layer provided on the second semiconductor part, the cap layer containing silicon oxide; and
a third semiconductor part provided on the cap layer.
2 . The semiconductor memory device according to claim 1 , wherein
the impurity semiconductor region contains arsenic.
3 . The semiconductor memory device according to claim 1 , wherein
the second select transistor is configured to cause Gate Induced Drain Leakage in response to a reverse bias voltage to be applied between the gate and a drain of the second select transistor.
4 . The semiconductor memory device according to claim 1 , wherein
the cap layer is doped with an impurity.
5 . The semiconductor memory device according to claim 4 , wherein
the impurity is one of phosphorus and arsenic.