Multilayer inner spacer for gate-all-around device
Semiconductor devices (e.g., gate-all-around (GAA) devices), process tools for manufacturing GAA devices and methods of manufacturing GAA devices and multilayer inner spacers for GAA devices are described. The multilayer inner spacer comprises an inner layer, a middle layer, and an outer layer within a superlattice structure formed on a top surface of a substrate. The superlattice structure has a plurality of semiconductor material layers (e.g., silicon germanium (SiGe)) and a corresponding plurality of channel layers (e.g., silicon (Si)) alternatingly arranged in a plurality of stacked pairs. In some embodiments, the methods are performed in situ in an integrated deposition and etch processing system.
1 . A method of manufacturing an electronic device, the method comprising:
forming a multilayer inner spacer comprising an inner layer, a middle layer, and an outer layer within a superlattice structure formed on a top surface of a substrate, the superlattice structure comprising a plurality of semiconductor material layers and a corresponding plurality of channel layers alternatingly arranged in a plurality of stacked pairs, the plurality of semiconductor material layers comprising silicon germanium (SiGe) and the corresponding plurality of channel layers comprising silicon (Si), forming the multilayer inner spacer comprising a thermal chemical vapor deposition (CVD) process at a temperature in a range of from 400° C. to 650° C., the thermal CVD process comprising:
depositing the inner layer on a recessed portion of the plurality of semiconductor material layers;
depositing the middle layer on the inner layer; and
depositing the outer layer on the middle layer, the outer layer adjacent a source region and a drain region, wherein one or more of the inner layer or the outer layer has a thickness in a range of from 0.5 nm to 2 nm and the middle layer has a thickness in a range of from 2 nm to 5 nm.
2 . The method of claim 1 , wherein one or more of the inner layer or the outer layer comprises a high-κ dielectric material.
3 . The method of claim 2 , wherein the high-κ dielectric material has a κ-value of greater than or equal to 6.
4 . The method of claim 2 , wherein the high-κ dielectric material comprises one or more of silicon nitride (SiN), silicon carbonitride (SiCN), or nitrogen-rich silicon oxycarbonitride (SiOCN).
5 . The method of claim 1 , wherein the middle layer comprises a low-κ dielectric material.
6 . The method of claim 5 , wherein the low-κ dielectric material has a κ-value of less than or equal to 4.2.
7 . The method of claim 5 , wherein the low-κ dielectric material comprises one or more of silicon (Si), silicon oxide (SiOx), doped silicon, doped silicon oxide, or spin-on dielectrics.
8 . The method of claim 1 , wherein the multilayer inner spacer is substantially free of seams and/or voids.
9 . The method of claim 1 , wherein the electronic device is a gate-all-around (GAA) device.
10 . The method of claim 1 , further comprising etching one or more of the outer layer or the middle layer.
11 . A method of manufacturing an electronic device, the method comprising:
forming a multilayer inner spacer comprising an inner layer, a middle layer, and an outer layer within a superlattice structure formed on a top surface of a substrate, the superlattice structure comprising a plurality of semiconductor material layers and a corresponding plurality of channel layers alternatingly arranged in a plurality of stacked pairs, the plurality of semiconductor material layers comprising silicon germanium (SiGe) and the corresponding plurality of channel layers comprising silicon (Si), forming the multilayer inner spacer comprising:
depositing the inner layer on a recessed portion of the plurality of semiconductor material layers;
optionally etching the inner layer;
depositing the middle layer on the inner layer;
etching a portion of the middle layer;
depositing the outer layer on the middle layer, the outer layer adjacent a source region and a drain region; and
etching the outer layer, wherein the inner layer, the middle layer, and the outer layer are each deposited by a thermal chemical vapor deposition process at a temperature in a range of from 400° C. to 650° C., one or more of the inner layer or the outer layer has a thickness in a range of from 0.5 nm to 2 nm, and the middle layer has a thickness in a range of from 2 nm to 5 nm.
12 . The method of claim 11 , performed in situ in an integrated deposition and etch processing system.
13 . The method of claim 11 , wherein one or more of the inner layer or the outer layer comprises a high-κ dielectric material.
14 . The method of claim 11 , wherein the middle layer comprises a low-κ dielectric material.
15 . The method of claim 11 , wherein the multilayer inner spacer is substantially free of seams and/or voids.
16 . A processing tool comprising:
a central transfer station comprising a robot configured to move a substrate;
a plurality of process stations, each process station connected to the central transfer station and providing a processing region separated from processing regions of adjacent process stations, the plurality of process stations comprising a chemical vapor deposition (CVD) chamber and an etch chamber; and
a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move the substrate between process stations, and to control a process cycle for manufacturing a multilayer inner spacer for a gate-all-around (GAA) device, the multilayer inner spacer comprising an inner layer, a middle layer, and an outer layer within a superlattice structure formed on a top surface of the substrate, the superlattice structure comprising a plurality of semiconductor material layers and a corresponding plurality of channel layers alternatingly arranged in a plurality of stacked pairs, the plurality of semiconductor material layers comprising silicon germanium (SiGe) and the corresponding plurality of channel layers comprising silicon (Si), the process cycle comprising forming the multilayer inner spacer by a thermal chemical vapor deposition (CVD) process at a temperature in a range of from 400° C. to 650° C., the thermal CVD process including:
depositing the inner layer on a recessed portion of the plurality of semiconductor material layers; depositing the middle layer on the inner layer; and depositing the outer layer on the middle layer, the outer layer adjacent a source region and a drain region, wherein one or more of the inner layer or the outer layer has a thickness in a range of from 0.5 nm to 2 nm and the middle layer has a thickness in a range of from 2 nm to 5 nm.