IP Library Granted Patent US 12,733,218
Granted Patent B2
US 12,733,218 · App. 18/160,162 · Granted Sep 8, 2026

Semiconductor device with a first parallel pn structure in the active region and a second parallel pn structure in the termination region wherein the depth of the second parallel structure becomes stepwise shallower towards the periphery

Inventor: Noriaki Yao (Matsumoto-city, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H10D62/111H10D30/0291H10D62/393H10P30/22
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,733,218
App. No.
18/160,162
Granted
Sep 8, 2026
Kind
B2
Abstract

A superjunction semiconductor device has: a semiconductor substrate of a first conductivity type; a buffer layer of the first conductivity type, provided on a front surface of the semiconductor substrate and having an impurity concentration lower than that of the semiconductor substrate; a drift layer of the first conductivity type, provided on the buffer layer and having an impurity concentration lower than that of the buffer layer; and a parallel pn structure having first column regions of the first conductivity type and second column regions of a second conductivity type repeatedly alternating one another in a direction parallel to the front surface. A subset of the first and second column regions are located in a termination structure portion and have depths that become shallower stepwise towards an end of the semiconductor substrate, where the second column regions are provided with bottoms thereof in the drift layer.

Claims (29)

1 . A superjunction semiconductor device having an active region and a termination structure portion disposed on an outer side of the active region so as to surround a periphery of the active region in a plan view of the superjunction semiconductor device, the superjunction semiconductor device comprising:

a semiconductor substrate of a first conductivity type;

a buffer layer of the first conductivity type, provided on a surface of the semiconductor substrate and having an impurity concentration that is lower than an impurity concentration of the semiconductor substrate;

a drift layer of the first conductivity type, provided on an upper surface of the buffer layer and having an impurity concentration that is lower than the impurity concentration of the buffer layer;

a plurality of first column regions of the first conductivity type and a plurality of second column regions of a second conductivity type, repeatedly alternating one another in a first direction parallel to the surface of the semiconductor substrate, to thereby form a first parallel pn structure in the active region, and form a second parallel pn structure in the termination structure portion;

a plurality of base regions of the second conductivity type, provided in the first parallel pn structure at a surface thereof;

a plurality of source regions of the first conductivity type, selectively provided in the base regions at surfaces thereof; and

a plurality of gate electrodes, each provided, via a gate electrode film, on a portion of the surface of one of the base regions, between one of the plurality of source regions and one of the plurality of first column regions, wherein

the plurality of first column regions and the plurality of second column regions of the first parallel pn structure are provided in the drift layer and reaching the buffer layer,

the plurality of first column regions and the plurality of second column regions of the second parallel pn structure have depths that become shallower stepwise in said first direction parallel to the surface of the semiconductor substrate toward an end portion of the semiconductor substrate,

bottoms of the plurality of second column regions of the second parallel pn structure are in the drift layer, and

at least one of the plurality of second column regions of the second parallel pn structure protrudes, in a second direction towards, and perpendicular to, the upper surface of the buffer layer, beyond two of the plurality of first column regions of the second parallel pn structure that are immediately adjacent to, and in the first direction sandwich, said at least one of the plurality of second column regions, said at least one of the plurality of second column regions having a bulged end.

2 . The superjunction semiconductor device according to claim 1 , wherein

the plurality of first column regions of the first parallel pn structure and the plurality of first column regions of the second parallel pn structure have a same first width, and

the plurality of second column regions of the first parallel pn structure and the plurality of second column regions of the second parallel pn structure have a same second width.

3 . The superjunction semiconductor device according to claim 1 , wherein

each of the plurality of second column regions has two portions, including

a first portion in contact with the drift layer, and

a second portion in contact with at least one of the plurality of first column regions, the first portion being wider than the second portion.

4 . The superjunction semiconductor device according to claim 1 , wherein

in the second parallel pn structure, the bottom of each of the plurality of second column regions, except for an innermost one thereof closest to the active region and an outermost one thereof closest to the end portion of the semiconductor substrate, is in the drift layer.

5 . The superjunction semiconductor device according to claim 1 , wherein

in the second parallel pn structure, at least one of the plurality of second column regions has a bottom that is shallower than that of an adjacent one of the plurality of second column regions, and

is in contact with the drift layer only at one side thereof in said first direction parallel to the surface of the semiconductor substrate.

6 . The superjunction semiconductor device according to claim 1 , wherein

each of the first parallel pn structure and the second parallel pn structure has a striped pattern in the plan view.

7 . The superjunction semiconductor device according to claim 1 , wherein

the impurity concentration of the buffer layer is higher than an impurity concentration of each of the plurality of first column regions.

8 . The superjunction semiconductor device according to claim 3 , wherein the first portion bulges toward the active region and the end portion of the semiconductor substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 26, 2023
From: YAO, NORIAKI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 062502/0320 →
Priority Claims (1)
JP 2022-040859 · Mar 16, 2022 · national
Continuity (1)
Related Publication 20230299131A1 · Sep 21, 2023
References Cited (16)
US 20030207536A1 · Miyasaka · 2003 [cited by examiner]
US 20070272979A1 · Saito · 2007 [cited by examiner]
US 20080315299A1 · Saito · 2008 [cited by examiner]
US 20140197477A1 · Onishi · 2014 [cited by examiner]
US 20150364577A1 · Nishimura et al. · 2015 [cited by applicant]
US 20150380542A1 · Weyers · 2015 [cited by examiner]
US 20170200784A1 · Shirakawa · 2017 [cited by examiner]
US 20210167167A1 · Kawada · 2021 [cited by examiner]
JP 2004022716A · 2004 [cited by examiner]
JP 2007335844A · 2007 [cited by applicant]
JP 2014138077A · 2014 [cited by applicant]
JP 2016021547A · 2016 [cited by applicant]
JP 2017126600A · 2017 [cited by applicant]
Translation of Sato (JP 2004-022716 A) (Year: 2004). [cited by examiner]
Translation of JP 200422716 A (Sato) (Year: 2004). [cited by examiner]
Office Action issued for corresponding Japanese Patent Application No. 2022-040859 dated Dec. 2, 2025. [cited by applicant]