Semiconductor device having macro cells
A semiconductor device includes a transistor having macro cells. A plurality of the macro cells include a first macro cell and a second macro cell. Each first and second macro cell includes trenches formed in a first main surface of a semiconductor substrate. The trenches pattern the semiconductor substrate into mesas and include a conductive trench, with a conductive material in the conductive trench being electrically connected to a terminal. A majority of all trenches of the first macro cell exclusively run in a first direction. A majority of all trenches of the second macro cell exclusively run in a second direction different from the first direction. At least one first macro cell is arranged adjacent to at least one second macro cell.
1 . A semiconductor device comprising a transistor, the transistor comprising a plurality of macro cells, the plurality of macro cells comprising first macro cells and second macro cells, each of the first and the second macro cells comprising:
a plurality of trenches formed in a first main surface of a semiconductor substrate, the trenches patterning the semiconductor substrate into mesas,
wherein the plurality of trenches comprises a conductive trench, a conductive material arranged in the conductive trench being electrically connected to a terminal,
wherein the trenches of the first macro cell run in a first direction,
wherein the trenches of the second macro cell run in a second direction different from the first direction,
wherein at least one of the first macro cells further comprises a first connection trench running in the first direction, a conductive material being arranged in the first connection trench,
wherein the conductive material of the first connection trench is electrically connected to a plurality of conductive trenches of at least one of the second macro cells,
wherein the terminal is a source terminal.
2 . The semiconductor device of claim 1 , wherein each of the first macro cells further comprises a first connection trench running in the first direction, a conductive material being arranged in the first connection trench, and wherein the conductive material of the first connection trench is electrically connected to a plurality of conductive trenches of the second macro cells.
3 . The semiconductor device of claim 1 , further comprising
an insulating layer over the semiconductor substrate; and
a first contact groove formed in the insulating layer and contacting a mesa of the first macro cells, a lateral extension of the first contact groove in the first direction being larger than a lateral extension of the first contact groove in the second direction.
4 . The semiconductor device of claim 3 , further comprising:
a second contact groove formed in the insulating layer and contacting a mesa of the second macro cells, a lateral extension of the second contact groove in the second direction being larger than a lateral extension of the second contact groove in the first direction.
5 . The semiconductor device of claim 3 , wherein the mesa contacted by the first contact groove comprises a doped semiconductor portion in contact with the first contact groove.
6 . The semiconductor device of claim 1 , wherein the trenches in the first macro cells and the trenches in the second macro cells further comprise a gate trench, and wherein a conductive material in the gate trenches is electrically connected to a gate terminal and insulated from adjacent semiconductor material of the semiconductor substrate.
7 . The semiconductor device of claim 1 , wherein the plurality of mesas comprise a dummy mesa that is disconnected from a terminal.
8 . The semiconductor device of claim 1 , wherein a number of trenches of the first macro cells is identical with a same number of trenches of the second macro cells.
9 . The semiconductor device of claim 1 , wherein the first and the second macro cells are arranged to form a checkerboard pattern.
10 . The semiconductor device of claim 9 , wherein the first and the second macro cells are arranged in columns and rows, an array of macro cells comprising an odd number of columns of macro cells and an odd number of rows of macro cells.
11 . The semiconductor device of claim 1 , wherein the trenches in the first macro cell and the trenches in the second macro cell further comprise a source trench, respectively, and wherein a conductive material in the source trench is electrically connected to a source terminal.
12 . The semiconductor device of claim 1 , wherein the trenches in the first macro cell and the trenches in the second macro cell further comprise a gate trench, respectively, and wherein a conductive material in the gate trench is electrically connected to a gate terminal.
13 . A semiconductor device comprising a transistor, the transistor comprising a comb cell comprising a plurality of trenches formed in a first main surface of a semiconductor substrate, the trenches patterning the semiconductor substrate into mesas, wherein:
the plurality of trenches comprises gate trenches and source trenches, a source connection trench, and a gate connection trench;
the source connection trench connects a conductive material in the source trenches to a source terminal;
the gate connection trench connects a conductive material in the gate trenches to a gate terminal;
the gate trenches and the source trenches run in a first direction; and
the source connection trench and the gate connection trench run in a second direction different from the first direction,
wherein the semiconductor device further comprises a passivation layer at least partly above a metallization layer at a frontside of the semiconductor device, the passivation layer comprising marker portions indicating the orientation of at least one of the macro cells.
14 . The semiconductor device of claim 13 , wherein the transistor comprises a plurality of comb cells arranged along the first direction, an intermediate region being arranged between two neighbouring comb cells, and wherein trenches are absent from the intermediate region.