IP Library Granted Patent US 12,733,255
Granted Patent B2
US 12,733,255 · App. 18/121,724 · Granted Sep 8, 2026

Integrated circuit structures having uniform grid metal gate and trench contact plug for tub gates with pyramidal channel structures

Inventors: Dan S. Lavric (Beaverton, OR); Shao Ming Koh (Tigard, OR); Anand S. Murthy (Portland, OR); Mauro J. Kobrinsky (Portland, OR)
Assignee: Intel Corporation
H10D84/856H10D30/43H10D30/6735H10D30/6757H10D62/121H10D64/017H10D64/021
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Quick Facts
Patent No.
US 12,733,255
App. No.
18/121,724
Granted
Sep 8, 2026
Kind
B2
Abstract

Integrated circuit structures having uniform grid metal gate and trench contact cut with pyramidal channel structures are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires having a pyramidal profile with a pyramid angle. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. The dielectric cut plug structure has a re-entrant profile with a cut angle laterally spaced apart from the pyramid angle of the pyramidal profile of the vertical stack of horizontal nanowires.

Claims (47)

1 . An integrated circuit structure, comprising:

a vertical stack of horizontal nanowires having a pyramidal profile with a pyramid angle;

a gate electrode over the vertical stack of horizontal nanowires;

a conductive trench contact adjacent to the gate electrode;

a dielectric sidewall spacer between the gate electrode and the conductive trench contact; and

a dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the dielectric cut plug structure having a re-entrant profile with a cut angle laterally spaced apart from the pyramid angle of the pyramidal profile of the vertical stack of horizontal nanowires.

2 . The integrated circuit structure of claim 1 , wherein the pyramid angle of the pyramidal profile of the vertical stack of horizontal nanowires is greater than the cut angle of the re-entrant profile of the dielectric cut plug structure.

3 . The integrated circuit structure of claim 1 , wherein the pyramid angle of the pyramidal profile of the vertical stack of horizontal nanowires is the same as the cut angle of the re-entrant profile of the dielectric cut plug structure.

4 . The integrated circuit structure of claim 1 , wherein the pyramid angle of the pyramidal profile of the vertical stack of horizontal nanowires is less than the cut angle of the re-entrant profile of the dielectric cut plug structure.

5 . The integrated circuit structure of claim 1 , further comprising:

a second dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

6 . The integrated circuit structure of claim 1 , further comprising:

an epitaxial source or drain structure at an end of the vertical stack of horizontal nanowires and beneath the conductive trench contact.

7 . The integrated circuit structure of claim 1 , further comprising:

a second gate electrode adjacent to the conductive trench contact on a side opposite the gate electrode, wherein the dielectric cut plug structure extends through the second gate electrode.

8 . The integrated circuit structure of claim 1 , further comprising:

a second conductive trench contact adjacent to the gate electrode on a side opposite the conductive trench contact, wherein the dielectric cut plug structure extends through the second conductive trench contact.

9 . The integrated circuit structure of claim 8 , further comprising:

a second gate electrode adjacent to the second conductive trench contact on a side opposite the gate electrode, wherein the dielectric cut plug structure extends through the second gate electrode.

10 . An integrated circuit structure, comprising:

a fin having a pyramidal profile with a pyramid angle;

a gate electrode over the fin;

a conductive trench contact adjacent to the gate electrode;

a dielectric sidewall spacer between the gate electrode and the conductive trench contact; and

a dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the dielectric cut plug structure having a re-entrant profile with a cut angle laterally spaced apart from the pyramid angle of the pyramidal profile of the fin.

11 . The integrated circuit structure of claim 10 , wherein the pyramid angle of the pyramidal profile of the fin is greater than the cut angle of the re-entrant profile of the dielectric cut plug structure.

12 . The integrated circuit structure of claim 10 , wherein the pyramid angle of the pyramidal profile of the fin is the same as the cut angle of the re-entrant profile of the dielectric cut plug structure.

13 . The integrated circuit structure of claim 10 , wherein the pyramid angle of the pyramidal profile of the fin is less than the cut angle of the re-entrant profile of the dielectric cut plug structure.

14 . The integrated circuit structure of claim 10 , further comprising:

a second dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.

15 . The integrated circuit structure of claim 10 , further comprising:

an epitaxial source or drain structure at an end of the fin and beneath the conductive trench contact.

16 . The integrated circuit structure of claim 10 , further comprising:

a second gate electrode adjacent to the conductive trench contact on a side opposite the gate electrode, wherein the dielectric cut plug structure extends through the second gate electrode.

17 . The integrated circuit structure of claim 10 , further comprising:

a second conductive trench contact adjacent to the gate electrode on a side opposite the conductive trench contact, wherein the dielectric cut plug structure extends through the second conductive trench contact.

18 . The integrated circuit structure of claim 17 , further comprising:

a second gate electrode adjacent to the second conductive trench contact on a side opposite the gate electrode, wherein the dielectric cut plug structure extends through the second gate electrode.

19 . A computing device, comprising:

a board; and

a component coupled to the board, the component including an integrated circuit structure, comprising:

a vertical stack of horizontal nanowires or a fin having a pyramidal profile with a pyramid angle;

a gate electrode over the vertical stack of horizontal nanowires or the fin;

a conductive trench contact adjacent to the gate electrode;

a dielectric sidewall spacer between the gate electrode and the conductive trench contact; and

a dielectric cut plug structure extending through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the dielectric cut plug structure having a re-entrant profile with a cut angle laterally spaced apart from the pyramid angle of the pyramidal profile of the vertical stack of horizontal nanowires or the fin.

20 . The computing device of claim 19 , wherein the component is a packaged integrated circuit die.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076008/0329 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 17, 2023
From: LAVRIC, DAN S.; KOH, SHAO MING; MURTHY, ANAND S.; KOBRINSKY, MAURO J.
To: INTEL CORPORATION
Reel/Frame 064282/0221 →
Continuity (1)
Related Publication 20240312996A1 · Sep 19, 2024
References Cited (1)
US 20230178623A1 · Li · 2023 [cited by examiner]