Single-photon avalanche diodes with hybrid trench isolation structures
Structures for a single-photon avalanche diode and methods of forming a structure for a single-photon avalanche diode. The structure comprises a semiconductor layer on a semiconductor substrate, a cathode comprising a first doped region in the semiconductor substrate, and an anode comprising a second doped region adjacent to a top surface of the semiconductor layer. The structure further comprises a first trench isolation structure including a first conductor layer extending from the top surface of the semiconductor layer through the semiconductor layer to the first doped region. The first conductor layer of the first trench isolation structure is connected to the first doped region. The structure further comprises a second trench isolation structure adjacent to the first trench isolation structure. The second trench isolation structure includes a second conductor layer extending from the top surface of the semiconductor layer fully through the first doped region.
1 . A structure for a single-photon avalanche diode, the structure comprising:
a semiconductor substrate having a top surface and a first doped region adjacent to the top surface of the semiconductor substrate;
a semiconductor layer on the top surface of the semiconductor substrate, the semiconductor layer having a top surface and a first trench extending from the top surface of the semiconductor layer fully through the semiconductor layer to a first depth in the semiconductor substrate, and the first trench has a first sidewall and a second sidewall;
a cathode including a portion of the first doped region in the semiconductor substrate;
an anode including a second doped region adjacent to the top surface of the semiconductor layer;
a first trench isolation structure inside the first trench, the first trench isolation region including a first conductor layer and a first dielectric layer extending from the top surface of the semiconductor layer through the semiconductor layer to the portion of the first doped region, the first dielectric layer having a first section on the first sidewall and a second section on the second sidewall, the first conductor layer is positioned between the first section of the first dielectric layer and the second section of the first dielectric layer, and the first conductor layer of the first trench isolation structure is electrically and physically connected to the portion of the first doped region; and
a second trench isolation structure adjacent to the first trench isolation structure, the second trench isolation structure including a second conductor layer extending from the top surface of the semiconductor layer fully through the first doped region.
2 . The structure of claim 1 wherein the second conductor layer of the second trench isolation structure is disposed in a second trench extending from the top surface of the semiconductor layer through the semiconductor layer to a second depth in the semiconductor substrate, and the second depth greater than the first depth.
3 . The structure of claim 2 wherein the first trench has a first width dimension at the top surface of the semiconductor layer, the second trench has a second width dimension at the top surface of the semiconductor layer, and the first width dimension is greater than the second width dimension.
4 . The structure of claim 2 further comprising:
a shallow trench isolation structure in the semiconductor layer,
wherein the first trench isolation structure extends through the shallow trench isolation structure into the semiconductor layer.
5 . The structure of claim 1 wherein the first trench isolation structure surrounds a first portion of the semiconductor layer that includes the second doped region.
6 . The structure of claim 4 wherein the second trench isolation structure surrounds the first trench isolation structure.
7 . The structure of claim 4 wherein the second trench isolation structure surrounds a second portion of the semiconductor layer that includes the first trench isolation structure.
8 . The structure of claim 1 further comprising:
a shallow trench isolation structure in the semiconductor layer,
wherein the first trench isolation structure extends through the shallow trench isolation structure into the semiconductor layer.
9 . The structure of claim 1 wherein the semiconductor layer has a thickness of about 8 microns to about 12 microns.
10 . The structure of claim 1 wherein the first conductor layer directly contacts the first doped region.
11 . The structure of claim 1 wherein the second trench isolation structure includes a second dielectric layer that electrically isolates the second conductor layer of the second trench isolation structure from the first doped region.
12 . The structure of claim 11 wherein the second conductor layer extends from the top surface of the semiconductor layer through the first doped region and into a portion the semiconductor substrate beneath the first doped region, and the second dielectric layer is disposed between the second conductor layer and the semiconductor substrate.
13 . The structure of claim 1 wherein the first conductor layer extends partially through the first doped region.
14 . The structure of claim 1 wherein the first doped region has doped region has n-type electrical conductivity, and further comprising:
a third doped region in the semiconductor substrate, the third doped region disposed between the first doped region and the top surface of the semiconductor layer, and the third doped region having p-type electrical conductivity,
wherein the first conductor layer of the first trench isolation structure extends fully through the third doped region to the first doped region.
15 . The structure of claim 1 wherein the first conductor layer and the second conductor layer comprise doped polysilicon, a metal, or a combination of doped polysilicon and metal.
16 . The structure of claim 1 further comprising:
a well in the semiconductor layer,
wherein the first doped region is disposed in the well.
17 . The structure of claim 1 wherein the first conductor layer directly contacts the first doped region.
18 . The structure of claim 1 wherein the first doped region has n-type electrical conductivity.
19 . A method of forming a structure for a single-photon avalanche diode, the method comprising:
forming a semiconductor layer on a top surface of a semiconductor substrate, wherein the semiconductor substrate includes a first doped region adjacent to the top surface of the semiconductor substrate;
forming a trench extending from a top surface of the semiconductor layer fully through the semiconductor layer to a depth in the semiconductor substrate, wherein the trench has a first sidewall and a second sidewall;
forming a cathode that includes a portion of the first doped region in the semiconductor substrate;
forming an anode that includes a second doped region adjacent to a top surface of the semiconductor layer;
forming a first trench isolation structure inside the trench, wherein the first trench isolation region includes a first conductor layer and a dielectric layer extending from the top surface of the semiconductor layer through the semiconductor layer to the portion of the first doped region, the dielectric layer has a first section on the first sidewall and a second section on the second sidewall, the first conductor layer is positioned between the first section of the dielectric layer and the second section of the dielectric layer, and the first conductor layer of the first trench isolation structure is electrically and physically connected to the portion of the first doped region; and
forming a second trench isolation structure adjacent to the first trench isolation structure, wherein the second trench isolation structure includes a second conductor layer extending from the top surface of the semiconductor layer fully through the first doped region.
20 . The structure of claim 18 wherein the semiconductor substrate has p-type electrical conductivity.