Image sensor including three substrates
An image sensor may include a first substrate having first and second surfaces opposite to each other and including a floating diffusion region provided near the first surface, a second substrate provided on the first surface of the first substrate, an intermediate substrate disposed between the first and second substrates, a first transistor disposed on a bottom surface of the intermediate substrate, a contact pattern electrically connecting the first transistor to the floating diffusion region, an upper interconnection layer provided on a bottom surface of the intermediate substrate, a lower interconnection layer between the upper interconnection layer and the second substrate, conductive pads electrically connecting the upper and lower interconnection layers, and a capacitor disposed on the second substrate. The contact pattern may penetrate the intermediate substrate and may be in contact with the floating diffusion region. The capacitor may be closer to the second substrate than the conductive pads.
1 . An image sensor, comprising:
a first substrate having a bottom surface and a top surface, which are opposite to each other, the first substrate including a floating diffusion region at the bottom surface of the first substrate and within the first substrate;
a second substrate below the bottom surface of the first substrate;
an intermediate substrate between the first substrate and the second substrate;
a first transistor on a bottom surface of the intermediate substrate;
a contact pattern electrically connecting the first transistor to the floating diffusion region;
an upper interconnection layer on the bottom surface of the intermediate substrate;
a lower semiconductor chip below the upper interconnection layer, the lower semiconductor chip including:
a lower interconnection layer, and
the second substrate,
wherein the lower interconnection layer is between the upper interconnection layer and the second substrate;
a first conductive pad at a bottom surface of the upper interconnection layer, the first conductive pad being bonded to a second conductive pad at a top surface of the lower interconnection layer, wherein the first conductive pad and the second conductive pad electrically connect the upper interconnection layer to the lower interconnection layer; and
a capacitor above the second substrate and below the upper interconnection layer,
wherein the contact pattern penetrates the intermediate substrate and contacts the floating diffusion region, and
wherein the capacitor is in the lower semiconductor chip and the capacitor is closer to the second substrate than the second conductive pad is to the second substrate.
2 . The image sensor as claimed in claim 1 , wherein the capacitor includes:
cylindrical bottom electrodes;
a top electrode on the cylindrical bottom electrodes;
a dielectric layer between the cylindrical bottom electrodes and the top electrode; and
an upper pad electrode on the top electrode.
3 . The image sensor as claimed in claim 1 , wherein:
the lower interconnection layer includes sequentially-stacked lower insulating layers, a mold insulating layer on the lower insulating layers, and lower interconnection patterns in the lower insulating layers, and
the capacitor is in the mold insulating layer.
4 . The image sensor as claimed in claim 1 , wherein:
the lower interconnection layer includes first and second lower insulating layers, a mold insulating layer between the first and second lower insulating layers, and lower interconnection patterns in the first and second lower insulating layers, and
the capacitor is in the mold insulating layer.
5 . The image sensor as claimed in claim 1 , wherein:
the upper interconnection layer includes sequentially-stacked upper insulating layers and upper interconnection patterns in the upper insulating layers,
the intermediate substrate includes at least one of silicon, silicon germanium, silicon carbide, or organic materials, and
each of the upper insulating layers includes silicon oxide.
6 . The image sensor as claimed in claim 1 , wherein:
the first substrate includes unit pixel regions, each of which includes a photoelectric conversion region, and
the capacitor vertically overlaps the photoelectric conversion region.
7 . The image sensor as claimed in claim 1 , wherein the first transistor includes an impurity region in the intermediate substrate.
8 . The image sensor as claimed in claim 1 , further comprising an insulating pattern covering a side surface of the contact pattern.
9 . The image sensor as claimed in claim 1 , further comprising a second transistor on a top surface of the second substrate, wherein:
the top surface of the second substrate faces the bottom surface of the first substrate, and
the second transistor is electrically connected to the capacitor.
10 . The image sensor as claimed in claim 1 , wherein:
the first conductive pad is in the upper interconnection layer and the second conductive pad is in the lower interconnection layer, and
the first conductive pad is in contact with the second conductive pad.
11 . An image sensor, comprising:
a first substrate having a bottom surface and a top surface, which are opposite to each other, the first substrate including unit pixel regions that each include a floating diffusion region at the bottom surface of the first substrate and within the first substrate;
an intermediate substrate below the bottom surface of the first substrate;
a transistor on a bottom surface of the intermediate substrate and electrically connected to the floating diffusion region through a contact pattern;
an upper interconnection layer below the intermediate substrate;
a lower semiconductor chip below the upper interconnection layer, the lower semiconductor chip including a lower interconnection layer electrically connected to the upper interconnection layer, and a second substrate below the lower interconnection layer; and
a first capacitor in the lower semiconductor chip,
wherein the contact pattern penetrates the intermediate substrate and has a side surface covered with an insulating pattern,
wherein the upper interconnection layer includes a first conductive pad at a bottom surface of the upper interconnection layer adjacent to an upper surface of the lower interconnection layer,
wherein the lower interconnection layer includes a second conductive pad at a top surface of the lower interconnection layer adjacent to a bottom surface of the upper interconnection layer, and
wherein the first conductive pad and the second conductive pad are in contact with each other.
12 . The image sensor as claimed in claim 11 , wherein the first capacitor is closer to the second substrate than the second conductive pad is to the second substrate.
13 . The image sensor as claimed in claim 11 , wherein the first capacitor is in the second substrate.
14 . The image sensor as claimed in claim 11 , wherein:
the lower interconnection layer includes sequentially-stacked lower insulating layers, a mold insulating layer on the lower insulating layers, and lower interconnection patterns in the lower insulating layers, and
the first capacitor is in the mold insulating layer.
15 . The image sensor as claimed in claim 11 , further comprising a second capacitor spaced apart from the first capacitor, wherein:
the first capacitor and the second capacitor include first bottom electrodes and second bottom electrodes, respectively, and
the first capacitor and the second capacitor share a dielectric layer on the first and second bottom electrodes, a top electrode on the dielectric layer, and a top electrode pad on the top electrode.
16 . An image sensor, comprising:
a first substrate having a bottom surface and a top surface, which are opposite to each other, the first substrate including a pixel array region, an optical black region, and a pad region;
a pixel isolation pattern on the pixel array region and in the first substrate to define unit pixel regions, the pixel isolation pattern including a first isolation pattern and a second isolation pattern interposed between the first isolation pattern and the first substrate;
a photoelectric conversion region in each of the unit pixel regions;
a floating diffusion region in each of the unit pixel regions and at the bottom surface of the first substrate and within the first substrate;
a transfer gate on the bottom surface of the first substrate;
an intermediate substrate below the bottom surface of the first substrate;
a first transistor on a bottom surface of the intermediate substrate, the first transistor including a first impurity region in the intermediate substrate;
an upper interconnection layer below the intermediate substrate, the upper interconnection layer including sequentially-stacked upper insulating layers and upper interconnection patterns in the upper insulating layers;
a contact pattern electrically connecting the first transistor to the floating diffusion region, the contact pattern penetrating the intermediate substrate and having a side surface covered with an insulating pattern;
an anti-reflection layer on the top surface of the first substrate;
a color filter on the anti-reflection layer;
a micro lens on the color filter;
a lower semiconductor chip below the upper interconnection layer, the lower semiconductor chip including:
a lower interconnection layer below the upper interconnection layer, and
a second substrate below the lower interconnection layer, the second substrate including a second transistor on a top surface of the second substrate,
conductive pads electrically connecting the upper interconnection layer to the lower interconnection layer, the conductive pads including a first conductive pad at a bottom surface of the upper interconnection layer and a second conductive pad at a top surface of the lower interconnection layer;
and
a capacitor in the lower interconnection layer of the lower semiconductor chip, the capacitor being closer to the second substrate than the second conductive pad is to the second substrate, the capacitor including:
bottom electrodes;
a top electrode on the bottom electrodes;
a dielectric layer between the bottom electrodes and the top electrode; and
an upper pad electrode on the top electrode.
17 . The image sensor as claimed in claim 16 , wherein the first conductive pad and the second conductive pad are in contact with each other.
18 . The image sensor as claimed in claim 16 , wherein:
the capacitor further includes a lower pad electrode electrically connected to the bottom electrodes, and
the bottom electrodes are cylindrical, and are arranged in a zigzag shape on the lower pad electrode when viewed in a plan view.
19 . The image sensor as claimed in claim 16 , wherein the capacitor vertically overlaps the photoelectric conversion region.
20 . The image sensor as claimed in claim 16 , wherein:
the intermediate substrate includes at least one of silicon, silicon germanium, silicon carbide, or organic materials, and
each of the upper insulating layers includes silicon oxide.