IP Library Granted Patent US 12,733,303
Granted Patent B2
US 12,733,303 · App. 17/903,126 · Granted Sep 8, 2026

IC package with micro LEDs

Inventors: Jacob Vehonsky (Gilbert, AZ); Onur Ozkan (Scottsdale, AZ); Vinith Bejugam (Chandler, AZ); Mao-Feng Tseng (Tempe, AZ); Nicholas Haehn (Scottsdale, AZ); Andrea Nicolas Flores (Chandler, AZ); Ali Lehaf (Phoenix, AZ); Benjamin Duong (Phoenix, AZ); Joshua Stacey (Chandler, AZ)
Assignee: Intel Corporation
H10H20/8506H10H20/01H10H20/856H10H20/857H10H20/0363H10H20/0364
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Quick Facts
Patent No.
US 12,733,303
App. No.
17/903,126
Granted
Sep 8, 2026
Kind
B2
Abstract

Embodiments of an integrated circuit (IC) package are disclosed. In some embodiments, the IC package includes a semiconductor die, a glass substrate, and a package substrate. The semiconductor die includes a micro light emitting diode (LED). The semiconductor die is at least partially embedded within the glass substrate and the glass substrate including a through glass via (TGV) embedded in the glass substrate wherein the TGV is electrically coupled to the semiconductor die to provide power to the micro LED. The package substrate that is coupled to the TGV.

Claims (38)

1 . An integrated circuit (IC) package, comprising:

a semiconductor die having a micro light emitting diode (LED) attached thereto;

a glass substrate, the semiconductor die being at least partially embedded within the glass substrate and the glass substrate including a through glass via (TGV) embedded in the glass substrate wherein the TGV is electrically coupled to and in contact with the semiconductor die to provide power to the micro LED; and

a package substrate that is coupled to the TGV.

2 . The IC package of claim 1 , wherein:

the glass substrate defines a first length parallel to a first axis and a first thickness parallel to a second axis that is orthogonal to the first axis,

the semiconductor die defines a second length parallel to the first axis and a second thickness parallel to the second axis.

3 . The IC package of claim 1 , wherein:

the glass substrate defines a first length parallel to a first axis and a first thickness parallel to a second axis that is orthogonal to the first axis,

the semiconductor die defines a second length parallel to the second axis and a second thickness parallel to the first axis.

4 . The IC package of claim 1 , wherein the TGV is directly connected to the semiconductor die.

5 . The IC package of claim 1 , further comprising a trace, wherein:

the semiconductor die includes a contact;

the trace connects the TGV to the contact of the semiconductor die.

6 . The IC package of claim 1 , wherein:

the glass substrate is attached to the package substrate;

a conductive via is integrated into the package substrate, wherein the conductive via is coupled to the TGV.

7 . The IC package of claim 6 , wherein the package substrate has a substrate body formed from a polymer.

8 . A method of manufacturing an integrated circuit (IC) package, comprising:

providing a semiconductor die having a micro light emitting diode (LED) attached thereto;

embedding the semiconductor die at least partially within a glass substrate;

forming a through glass via (TGV) embedded in the glass substrate such that the TGV is electrically coupled to and in contact with the semiconductor die to provide power the micro LED; and

providing a package substrate;

coupling the package substrate to the TGV.

9 . The method of claim 8 , wherein:

the glass substrate defines a first length parallel to a first axis and a first thickness parallel to a second axis that is orthogonal to the first axis,

the semiconductor die defines a second length parallel to the first axis and a second thickness parallel to the second axis.

10 . The method of claim 8 , wherein:

the glass substrate defines a first length parallel to a first axis and a first thickness parallel to a second axis that is orthogonal to the first axis,

the semiconductor die defines a second length parallel to the second axis and a second thickness parallel to the first axis.

11 . The method of claim 8 , wherein the TGV is directly connected to the semiconductor die.

12 . The method of claim 8 , wherein the glass substrate defines a first surface and a second surface opposite to the first surface and the package substrate comprises a first package substrate, the method further comprising:

attaching the first package substrate on and under the first surface;

attaching a second package substrate on and over the second surface.

13 . The method of claim 8 , further comprising:

forming a conductive via integrated into the package substrate

attaching the package substrate to the glass substrate so that the conductive via is coupled to the TGV.

14 . The method of claim 13 , wherein the package substrate has a substrate body formed from a polymer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076008/0329 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2023
From: VEHONSKY, JACOB; OZKAN, ONUR; BEJUGAM, VINITH; TSENG, MAO-FENG; HAEHN, NICHOLAS; NICOLAS FLORES, ANDREA; LEHAF, ALI; DUONG, BENJAMIN; STACEY, JOSHUA
To: INTEL CORPORATION
Reel/Frame 062944/0405 →
Continuity (1)
Related Publication 20240079530A1 · Mar 7, 2024
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