Substrate including test circuit and substrate test apparatus including the substrate
Provided are a substrate including a test circuit capable of testing a damaged state thereof. The substrate includes a substrate body, and a test circuit arranged on at least one of an upper surface and a lower surface of the substrate body, wherein the test circuit includes two contact pads and at least one test wiring, the two contact pads being at an end portion of the substrate body and configured to contact two probe pins of a test element, the test wiring extending to surround an outer periphery portion of the substrate body and configured to connect the two contact pads to each other, and wherein, in an electrical test using the test element, when the test wiring is in a closed state, the substrate body is determined as normal, and when the test wiring is in an open state, the substrate body is determined as defective.
1 . A substrate including a test circuit, the substrate comprising:
a substrate body; and
the test circuit on at least one of an upper surface and a lower surface of the substrate body, wherein the test circuit comprises two contact pads and at least one test wiring, the two contact pads being at an end portion of the substrate body and configured to contact two probe pins of a test element, the at least one test wiring extending to surround a first outer periphery portion of the substrate body and configured to connect the two contact pads to each other, the at least one test wiring being a single integral body, and
in an electrical test using the test element, when the at least one test wiring is in a closed state, the substrate body is determined as normal, and when the at least one test wiring is in an open state, the substrate body is determined as defective.
2 . The substrate of claim 1 , wherein
the substrate body comprises a printed circuit board (PCB) of a rectangular shape extending in a first direction,
the two contact pads are adjacent to a first short side among two short sides, and are at a central portion of the first short side in a second direction perpendicular to the first direction, and
the at least one test wiring extends from a first contact pad among the two contact pads, along a first portion of the first short side, a first long side among two long sides, a second short side among the two short sides, a second long side among the two long sides, and a second portion of the first short side, to a second contact pad among the two contact pads.
3 . The substrate of claim 2 , wherein
the substrate comprises a wire bonding substrate configured to wire-bond first semiconductor chips in a two-dimensional array structure on at least one surface of the substrate body, or
the substrate comprises a die attachment substrate configured to attach second semiconductor chips in a two-dimensional array structure on the at least one surface of the substrate body.
4 . The substrate of claim 2 , wherein the substrate further comprises semiconductor chips in a two-dimensional array structure on at least one surface of the substrate body.
5 . The substrate of claim 1 , wherein
the substrate body comprises a wafer of a circular shape,
the two contact pads are on a partial area of a second outer periphery portion of the wafer that is adjacent to a flat-zone or a notch of the wafer, and
the at least one test wiring extends from a first contact pad among the two contact pads, along the second outer periphery portion of the wafer in the circular shape, to a second contact pad among the two contact pads.
6 . The substrate of claim 5 , wherein the substrate comprises a plurality of semiconductor chips in a two-dimensional array structure in the substrate body.
7 . The substrate of claim 1 , wherein
the closed state is a first state in which a first current flows when the first current is applied via the test element, and
the open state is a second state in which a second current does not flow when the second current is applied via the test element.
8 . A substrate test apparatus comprising:
a substrate including a substrate body, and a test circuit on at least one of an upper surface and a lower surface of the substrate body; and
a test element configured to test the substrate,
wherein the test circuit comprises two contact pads and at least one test wiring, the two contact pads being at an end portion of the substrate body and configured to contact two probe pins of the test element, the at least one test wiring extending to surround a first outer periphery portion of the substrate body and configured to connect the two contact pads to each other, the at least one test wiring being a single integral body, and
in an electrical test using the test element, the substrate test apparatus is configured to determine the substrate as normal when the at least one test wiring is in a closed state, and determine the substrate as defective when the at least one test wiring is in an open state.
9 . The substrate test apparatus of claim 8 , wherein
the substrate body comprises a printed circuit board (PCB) of a rectangular shape extending in a first direction,
the two contact pads are adjacent to a first short side among two short sides, and are at a central portion of the first short side in a second direction vertical to the first direction, and
the at least one test wiring extends from a first contact pad among the two contact pads, along a first portion of the first short side, a first long side among two long sides, a second short side among the two short sides, a second long side among the two long sides, and a second portion of the first short side, to a second contact pad among the two contact pads.
10 . The substrate test apparatus of claim 9 , wherein
the test element is in a gripper that is configured to grip and move the substrate body, and
when the gripper grips the substrate body, the test element is configured to perform the electrical test.
11 . The substrate test apparatus of claim 9 , wherein
the substrate comprises a wire bonding substrate configured to wire-bond first semiconductor chips in a two-dimensional array structure on at least one surface of the substrate body, or
the substrate comprises a die attachment substrate configured to attach second semiconductor chips in a two-dimensional array structure on the at least one surface of the substrate body.
12 . The substrate test apparatus of claim 9 , wherein the substrate further comprises semiconductor chips in a two-dimensional array structure on at least one surface of the substrate body.
13 . The substrate test apparatus of claim 8 , wherein
the substrate body comprises a wafer of a circular shape,
the two contact pads are on a partial area of a second outer periphery portion of the wafer that is adjacent to a flat-zone or a notch of the wafer, and
the at least one test wiring extends from a first contact pad among the two contact pads, along the second outer periphery portion of the wafer in the circular shape, to a second contact pad among the two contact pads.
14 . The substrate test apparatus of claim 13 , wherein
the test element is on a wafer movement apparatus that is configured to contact at least a portion of the substrate body and move the substrate body, and
when the wafer movement apparatus contacts the substrate body, the test element is configured to perform the electrical test.
15 . The substrate test apparatus of claim 13 , wherein the substrate comprises a plurality of semiconductor chips in a two-dimensional array structure in the substrate body.
16 . A substrate test apparatus comprising:
a substrate including a substrate body and a test circuit, the test circuit on at least one of an upper surface and a lower surface of the substrate body;
a test element configured to test the substrate; and
a substrate movement apparatus configured to move the substrate, the substrate movement apparatus having at least some components of the test element thereon,
wherein the test circuit comprises two contact pads and at least one test wiring, the two contact pads being at an end portion of the substrate body and configured to contact two probe pins of the test element, the at least one test wiring extending to surround an outer periphery portion of the substrate body and configured to connect the two contact pads to each other, the at least one test wiring being a single integral body,
when the substrate movement apparatus contacts the substrate, the test element is configured to perform an electrical test on the substrate, and
in the electrical test, the substrate test apparatus is configured to determine the substrate as normal when the at least one test wiring is in a closed state, and determine the substrate as defective when the at least one test wiring is in an open state.
17 . The substrate test apparatus of claim 16 , wherein
the substrate body comprises a printed circuit board (PCB) of a rectangular shape extending in a first direction,
the substrate movement apparatus comprises a gripper configured to grip and move the substrate body, and
when the gripper grips the substrate body, the test element is configured to perform the electrical test.
18 . The substrate test apparatus of claim 16 , wherein
the substrate comprises a wire bonding substrate configured to wire-bond first semiconductor chips in a two-dimensional array structure on at least one surface of the substrate body, or
the substrate comprises a die attachment substrate that is configured to attach second semiconductor chips in a two-dimensional array structure on the at least one surface of the substrate body.
19 . The substrate test apparatus of claim 16 , wherein
the substrate body comprises a wafer of a circular shape,
the substrate movement apparatus comprises a wafer movement apparatus configured to contact at least a portion of the substrate body and move the substrate body, and
when the wafer movement apparatus contacts the substrate body, the test element is configured to perform the electrical test.
20 . The substrate test apparatus of claim 16 , wherein the substrate further comprises:
first semiconductor chips in a two-dimensional array structure on at least one surface of the substrate body, or
second semiconductor chips in a two-dimensional array structure in the substrate body.