Selective bottomless graphene lined interconnects
Embodiments disclosed herein include integrated circuit structures and methods of forming such structures. In an embodiment, an integrated circuit structure comprises a dielectric layer with a first surface and a second surface, and an opening through the dielectric layer. In an embodiment, the opening is defined by sidewalls. In an embodiment, a graphene liner contacts the first surface of the dielectric layer and the sidewalls of the opening. In an embodiment, a conductive material at least partially fills a remainder of the opening.
1 . An integrated circuit structure, comprising:
a dielectric layer with a first surface and a second surface;
an opening through the dielectric layer, wherein the opening is defined by sidewalls;
a graphene liner contacting the first surface of the dielectric layer and the sidewalls of the opening, wherein the graphene liner on the sidewalls of the opening does not cover the sidewalls at a bottom region of the opening; and
a conductive material that at least partially fills a remainder of the opening.
2 . The integrated circuit structure of claim 1 , further comprising:
a trace below and in contact with the conductive material.
3 . The integrated circuit structure of claim 1 , wherein the conductive material contacts the sidewalls of the opening at the bottom region of the opening.
4 . The integrated circuit structure of claim 1 , wherein a height of the bottom region of the opening is approximately 1 nm or less.
5 . The integrated circuit structure of claim 1 , wherein a width of the opening is approximately 20 nm or less.
6 . The integrated circuit structure of claim 1 , wherein the conductive material is a via.
7 . The integrated circuit structure of claim 1 , wherein a thickness of the liner is approximately 6 angstroms or less.
8 . An integrated circuit structure, comprising:
a first trace, wherein the first trace is lined with a first graphene liner;
a second trace, wherein the second trace is lined with a second graphene liner; and
a via between the first trace and the second trace, wherein the via is lined with a third graphene liner, wherein a bottom of the via contacts the second trace, wherein a bottom surface of the third graphene liner is above the bottom of the via.
9 . The integrated circuit structure of claim 8 , wherein the first graphene liner is along sidewalls and a bottom surface of the first trace, and wherein the second graphene liner is along sidewalls and a bottom surface of the second trace.
10 . The integrated circuit structure of claim 8 , wherein the via has a thickness that is approximately 20 nm or less.
11 . The integrated circuit structure of claim 8 , wherein sidewalls of the via are tapered.
12 . The integrated circuit structure of claim 8 , wherein the first trace is substantially orthogonal to the second trace.
13 . The integrated circuit structure of claim 8 , wherein the first graphene liner is contacted by the third graphene liner.
14 . The integrated circuit structure of claim 13 , wherein the third graphene liner does not contact the second graphene liner.
15 . The integrated circuit structure of claim 8 , wherein the first graphene liner, the second graphene liner, and the third graphene liner have thicknesses that are approximately 6 angstroms or less.
16 . A method of forming an integrated circuit structure, comprising:
forming an opening in a dielectric layer, wherein the opening exposes a top surface of a first conductive material;
forming a self-assembled monolayer (SAM) over the first conductive material;
treating the dielectric layer with a plasma;
forming a graphene liner over sidewalls of the opening, wherein the graphene liner on the sidewalls of the opening does not cover the sidewalls at a bottom region of the opening;
removing the SAM; and
filling the opening with a second conductive material.
17 . The method of claim 16 , wherein the graphene liner has a thickness that is approximately 6 angstroms or less.
18 . The method of claim 16 , wherein a width of the opening is approximately 20 nm or less.
19 . The method of claim 16 , wherein the SAM has a thickness that is approximately 1 nm or less.
20 . The method of claim 16 , wherein the plasma treatment is a halogen-based plasma treatment.
21 . The method of claim 16 , wherein the first conductive material is a trace, and wherein the second conductive material is a via.
22 . An electronic system, comprising:
a board;
a package substrate coupled to the board; and
a die coupled to the package substrate, wherein the die comprises an integrated circuit structure, wherein the integrated circuit structure comprises:
a first trace, wherein the first trace comprises a first graphene liner that is U-shaped;
a second trace, wherein the second trace comprises a second graphene liner that is U-shaped; and
a via between the first trace and the second trace, wherein the via comprises a third graphene liner that surrounds a perimeter of the via, wherein a bottom of the third graphene line is above a bottom surface of the via.