IP Library Granted Patent US 12,733,479
Granted Patent B2
US 12,733,479 · App. 17/935,999 · Granted Sep 8, 2026

Integrated circuit (IC) device with multilayer metal line

Inventors: Ilya V. Karpov (Portland, OR); Shafaat Ahmed (Albuquerque, NM); Matthew V. Metz (Portland, OR); Darren Anthony Denardis (Albuquerque, NM); Nafees Aminul Kabir (Hillsboro, OR); Tristan A. Tronic (Aloha, OR)
Assignee: Intel Corporation
H10W20/42H10W20/056H10W20/077H10W20/425H10W20/435
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Quick Facts
Patent No.
US 12,733,479
App. No.
17/935,999
Granted
Sep 8, 2026
Kind
B2
Abstract

An IC device includes a multilayer metal line that is at least partially surrounded by one or more electrical insulators. The multilayer metal line may be formed by stacking four layers on top of one another. The four layers may include a first layer between a second layer and a third layer. The first layer may include Al. The second or third layer may include W. The fourth layer may be a conductive or dielectric layer. The second layer, third layer, and fourth layer can protect the first layer from defects in Al core layer during fabrication or operation of the multilayer metal line. Substrative etch may be performed on the stack of the four layers to form openings. An electrical insulator may be deposited into to the openings to form multiple metal lines that are separated by the electrical insulator. A via may be formed over the third layer.

Claims (43)

1 . An integrated circuit (IC) device, comprising:

a first structure comprising a first layer, a second layer, and a third layer, wherein the first layer is between the second layer and the third layer in a first direction, the first layer comprises a first metal, and the second layer or the third layer comprises a second metal that is different from the first metal; and

a second structure at least partially wrapping around the first structure;

a third structure comprising an electrical insulator;

a fourth structure comprising another electrical insulator, wherein at least part of the fourth structure is over the third structure in the first direction; and

a fifth structure comprising a metal, wherein a first portion of the fifth structure is at least partially wrapped around by the fourth structure and another portion of the fifth structure is at least partially wrapped around by the third structure,

wherein a portion of the second structure is between the first structure and the third structure in a second direction, a height of the second structure in the first direction is at least equal to a height of the first layer in the first direction, and the second direction is orthogonal to the first direction.

2 . The IC device according to claim 1 , wherein the first structure further comprises a fourth layer, at least a portion of the second layer is between the fourth layer and the first layer in the first direction, and the fourth layer comprises a dielectric material or a conductive material.

3 . The IC device according to claim 2 , wherein a height of the fourth layer in the first direction is between about 5 and 20 nanometers.

4 . The IC device according to claim 2 , wherein a width of the second layer in the second direction is smaller than a width of the third layer in the second direction.

5 . The IC device according to claim 2 , wherein the third layer is connected to a via, and the via is connected to a terminal of a semiconductor device.

6 . The IC device according to claim 2 , wherein another portion of the second layer is connected to a via, the via is connected to a fourth structure, and the fourth structure comprises one or more metal layers.

7 . The IC device according to claim 1 , wherein a height of the first layer in the first direction is between about 15 and 40 nanometers.

8 . The IC device according to claim 1 , wherein a width of the first layer in the second direction is not greater than 15 nanometers.

9 . The IC device according to claim 1 , wherein a height of the second layer or the third layer in the first direction is between about 2 and 5 nanometers.

10 . The IC device according to claim 1 , wherein the first metal includes aluminum.

11 . An integrated circuit (IC) device, comprising:

a first layer comprising a first metal;

a second layer comprising a second metal, wherein the second layer comprises a first portion and a second portion;

a third layer comprising a third metal;

a fourth layer comprising a dielectric material, wherein the fourth layer is over the first portion of the second layer;

a fifth layer comprising another dielectric material, wherein at least part of the fifth layer is over the fourth layer;

a via over the second portion of the second layer, the via comprising a metal,

wherein the first layer is between the second layer and the third layer, wherein the first metal is different from the second metal or the third metal, and wherein a portion of the via is at least partially wrapped around by the fourth layer and another portion of the via is at least partially wrapped around by the fifth layer.

12 . The IC device according to claim 11 , further comprising:

a sixth layer, the sixth layer wrapping around at least part of a combination of the first layer, the second layer, and the third layer.

13 . The IC device according to claim 11 , wherein the first layer is between the second layer and the third layer in a first direction, and a width of the second layer in a second direction orthogonal to the first direction is smaller than a width of the third layer in the second direction.

14 . The IC device according to claim 11 , wherein a distance between the second layer and the third layer is between about 15 and 40 nanometers.

15 . The IC device according to claim 11 , wherein the third layer is connected to an additional via, the additional via is connected to a terminal of a semiconductor device.

16 . A method for forming an integrated circuit (IC) device, comprising:

forming a first layer between a second layer and a third layer, wherein the first layer comprises a first metal, and the second or third layer comprises a second metal;

forming a fourth layer over the second layer, wherein the fourth layer comprises a dielectric material;

after forming the fourth layer, forming an opening through the first layer, the second layer, the third layer, and the fourth layer;

forming a fifth layer in the opening, wherein the fifth layer at least partially wraps around the first layer;

after forming the fifth layer, providing an electrical insulator to the opening;

forming a sixth layer over the fourth layer, wherein the sixth layer comprises another dielectric material;

forming a first opening by removing a portion of the sixth layer through a first etch;

forming a second opening by removing a portion of the fourth layer through a second etch, wherein the first opening is over the second opening; and

providing a metal to the first opening and the second opening.

17 . The method according to claim 16 , wherein forming the first layer between the second layer and the third layer comprises:

forming the first layer between the second layer and the third layer at a pressure that is between about 10 −9 to 10 −6 Torr.

18 . The method according to claim 16 , wherein a distance between the second layer and the third layer is between about 15 and 40 nanometers.

19 . The method according to claim 16 , wherein the first metal is aluminum.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 14, 2026
From: INTEL CORPORATION
To: INTEL FOUNDRY IP LLC
Reel/Frame 076007/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2023
From: AHMED, SHAFAAT; KARPOV, ILYA V.; METZ, MATTHEW V.; DENARDIS, DARREN ANTHONY; KABIR, NAFEES AMINUL; TRONIC, TRISTAN A.
To: INTEL CORPORATION
Reel/Frame 062918/0852 →
Continuity (1)
Related Publication 20240105588A1 · Mar 28, 2024
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