IP Library › Granted Patent US 12,733,542
Granted Patent B2
US 12,733,542 · App. 17/657,760 · Granted Sep 8, 2026

Three-dimensional (3D) integrated circuit (IC) (3DIC) package employing a redistribution layer (RDL) interposer facilitating semiconductor die stacking, and related fabrication methods

Inventors: Stanley Seungchul Song (San Diego, CA); Jonghae Kim (San Diego, CA); Je-Hsiung Lan (San Diego, CA); Periannan Chidambaram (San Diego, CA)
Assignee: QUALCOMM INCORPORATED
H10W90/00H10W20/023H10W20/20H10W70/05H10W70/09H10W70/093H10W70/611H10W70/614H10W70/635H10W70/65H10W70/6528H10W90/271H10W90/297
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Quick Facts
Patent No.
US 12,733,542
App. No.
17/657,760
Granted
Sep 8, 2026
Kind
B2
Abstract

Three-dimensional (3D) integrated circuit (IC) (3DIC) package employing a redistribution layer (RDL) interposer facilitating semiconductor die (“die”), and related fabrication methods. The 3DIC package includes an RDL interposer that has one or more RDL metallization layers formed adjacent to a first, bottom die(s). A second, top die(s) is stacked on the RDL interposer. The RDL interposer provides an extended die area that the top die can be coupled so that the fabrication process of the 3DIC package is independent die sizes. The bottom die(s) can be singulated and disposed in an RDL metallization layer(s) as part of a reconstituted RDL interposer regardless of whether the top die(s) is greater than or less than the size of the bottom die(s). Also, the RDL interposer being the substrate in which the bottom die(s) is disposed and top die(s) is coupled provides efficient signal routing paths to the top and bottom dies.

Claims (49)

1 . An integrated circuit (IC) package, comprising:

an interposer, comprising:

a first surface and a second surface opposing the first surface; and

one or more redistribution layers (RDLs) between the first surface and the second surface, the one or more RDLs comprising:

a first RDL comprising:

a first metal interconnect; and

a second metal interconnect;

a first die disposed in the interposer, the first die comprising a first die interconnect embedded in the first die and coupled to the first metal interconnect; and

a second die coupled to the first surface of the interposer, the second die comprising a second die interconnect embedded in the second die, wherein the first die interconnect of the first die is directly bonded to the second die interconnect of the second die, coupling the second die interconnect to the first metal interconnect, the second die further comprising:

an outer die interconnect embedded in the second die and coupled to the second metal interconnect, the second metal interconnect coupled to a region of the first RDL laterally offset from a footprint of the second die on the first surface of the interposer.

2 . The IC package of claim 1 , wherein:

the interposer extends in a first direction;

the second surface is opposing the first surface in a second direction orthogonal to the first direction; and

the one or more RDLs are disposed between the first surface and the second surface in the second direction.

3 . The IC package of claim 1 , wherein the first die is adjacent to the first RDL.

4 . The IC package of claim 1 , wherein:

the one or more RDLs further comprises a second RDL; and

the first die further comprises a third die interconnect coupled to a third metal interconnect in the second RDL.

5 . The IC package of claim 1 , wherein the first metal interconnect is coupled to the second metal interconnect.

6 . The IC package of claim 1 , wherein:

the second die shares a first common plane with the first die; and

a fifth die interconnect of the second die is bonded to a third die interconnect of the first die.

7 . The IC package of claim 1 , wherein:

the first die comprises a first active face adjacent to the first surface and a third die interconnect exposed from the first active face;

the second die comprises a second active face adjacent to the first surface, wherein a fifth die interconnect is exposed from the second active face; and

the fifth die interconnect of the second die is bonded to the third die interconnect of the first die.

8 . The IC package of claim 1 , wherein:

the first die comprises a first inactive face adjacent to the first surface and a third die interconnect exposed from the first inactive face;

the second die comprises a second active face adjacent to the first surface, wherein a fifth die interconnect is exposed from the second active face; and

the fifth die interconnect of the second die is bonded to the third die interconnect of the first die.

9 . The IC package of claim 1 , further comprising a first via disposed through the first die;

wherein the second die interconnect of the second die is coupled to the first via.

10 . The IC package of claim 1 , further comprising;

a third die coupled to the first surface of the interposer and including a sixth die interconnect;

a first via extending from the first surface of the interposer to the second surface of the interposer, wherein the sixth die interconnect of the third die is coupled to the first via.

11 . The IC package of claim 1 , further comprising a third die coupled to a first area on the first surface of the interposer outside a second area of the first die in the interposer;

wherein the third die comprises a third die interconnect coupled to the second metal interconnect of the first RDL.

12 . The IC package of claim 1 , further comprising a third die disposed in the first RDL,

the third die comprising a seventh die interconnect coupled to the second metal interconnect in the first RDL.

13 . The IC package of claim 12 , wherein the third die is not communicatively coupled to the second die.

14 . The IC package of claim 1 , further comprising:

one or more external interconnects coupled to a bottom surface of the interposer, the one or more external interconnects each coupled to one or more second metal interconnects in the first RDL; and

a package substrate coupled to the one or more external interconnects.

15 . The IC package of claim 14 , wherein the one or more external interconnects comprise one or more ball grid array (BGA) interconnects.

16 . The IC package of claim 1 , wherein:

the second die further comprises an integrated capacitor;

the second die further comprises a third die interconnect; and

the third die interconnect is coupled to the integrated capacitor and to the second metal interconnect of the first RDL.

17 . The IC package of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone; a cellular phone; a smart phone; a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; avionics systems; a drone; and a multicopter.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2022
From: SONG, STANLEY SEUNGCHUL; KIM, JONGHAE; LAN, JE-HSIUNG; CHIDAMBARAM, PERIANNAN
To: QUALCOMM INCORPORATED
Reel/Frame 061270/0228 →
Continuity (1)
Related Publication 20230317677A1 · Oct 5, 2023
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