Automated multi-stage design flow based on final quality of result

1 . A method comprising:

executing a plurality of design iterations for a design flow for a circuit; wherein:

the design flow comprises a sequence of at least two stages, and each stage produces an output design of the circuit from an input design of the circuit in accordance with parameters for that stage;

the design iterations comprise selecting parameter values for slices of one or more stages of the design flow;

the design iterations are executed according to a tree search strategy, in which the stages of the design flow represent different layers of the tree; and

the design iterations for a first one of the slices comprise selecting parameter values for a non-final stage of the design flow based on a final quality of result (QoR) of the design flow; and

adapting, by a processing device, the design iterations for the first slice based on final QoRs produced by the design iterations.

2 . The method of claim 1 wherein the design iterations comprise selecting parameter values for each of the non-final stages of the design flow based on the final QoR of the design flow.

3 . The method of claim 2 further comprising:

adapting the design iterations that select parameter values based on the final QoR of the design flow, based on final QoRs produced by the design iterations.

4 . The method of claim 1 wherein:

the stages include synthesis and placement, clock tree synthesis and routing; and

the final QoR is a function of routing congestion, total negative slack (TNS), total power and total standard cell area.

5 . The method of claim 1 wherein the final QoR comprises an aggregate of at least two performance metrics of the output design of the circuit from a final stage of the design flow.

6 . The method of claim 1 wherein the design iterations for the first slice select parameter values for all stages in the first slice based on the final QoR of the design flow.

7 . The method of claim 1 wherein adapting the design iterations for the first slice is further based on final QoRs produced by design iterations for other slices.

8 . The method of claim 1 further comprising:

for all design iterations that are based on the final QoR, adapting all such design iterations based on final QoRs produced by all complete sequences of stages from the design iterations.

9 . A system comprising:

a memory storing instructions; and

a processing device, coupled with the memory and to execute the instructions, the instructions when executed cause the processing device to:

receive instructions relating to design iterations for a design flow to design a circuit, wherein the design flow comprises a sequence of at least two stages, and each stage produces an output design of the circuit from an input design of the circuit in accordance with parameters for that stage;

execute a plurality of design iterations in accordance with the instructions; wherein each design iteration selects parameter values for a subflow of one or more stages, and the design iterations include final QoR-based design iterations that select parameter values for a non-final stage of the design flow based on a final QoR of the design flow, and the instructions specify parameter values that are given priority during the design iterations; and

adapting the final QoR-based design iterations based on the final QoRs produced in previously executed design iterations by sequences that include all stages in the design flow.

10 . The system of claim 9 wherein the instructions specify compute limits on the design iterations.

11 . The system of claim 9 wherein the instructions specify stop rules for early termination of design iterations.

12 . The system of claim 9 wherein the design flow includes a plurality of sessions that execute the plurality of design iterations, and the instructions specify which stages are included in the subflow for each session.

13 . The system of claim 9 wherein the instructions specify limits on a number of design iterations that are executed.

14 . The system of claim 9 wherein the instructions specify a tree search strategy for the design iterations on a scale ranging from a depth-first search to a breadth-first search.

15 . The system of claim 9 wherein the instructions specify the stages in the design flow, parameters for the stages, compute limits on the design iterations, the final QoR, and a goal for the final QoR.

16 . A non-transitory computer readable medium comprising stored instructions, which when executed by a processing device, cause the processing device to:

execute a plurality of design iterations for a design flow to design a circuit, wherein the design flow comprises a sequence of at least two stages, each stage produces an output design of the circuit from an input design of the circuit in accordance with parameters for that stage, each design iteration selects parameter values for a subflow of one or more stages, and the design iterations include final QoR-based design iterations that select parameter values for a non-final stage of the design flow based on a final QoR of the design flow; and

adapting the final QoR-based design iterations based on the final QoRs produced in previously executed design iterations by sequences that include all stages in the design flow; and

in addition to the final QoR-based design iterations, the design iterations also include local design iterations that select parameter values for a non-final stage of the design flow based on an intermediate quality of result (QoR) for that non-final stage.

17 . The non-transitory computer readable medium of claim 16 wherein most of the local design iterations are executed before most of the final QoR-based design iterations.

18 . The non-transitory computer readable medium of claim 16 wherein adapting the final QoR-based design iterations uses machine learning.