IP Library › Granted Patent US 12,740,414
Granted Patent B2
US 12,740,414 · App. 17/660,485 · Granted Sep 15, 2026

Semiconductor packaging

Inventors: Hyoungsoon Lee (Seongnam-si, KR); Jung Bin In (Seoul, KR); Yunseo Kim (Incheon, KR); Daeyoung Kong (Incheon, KR); Kiwan Kim (Anyang-si, KR); Jungbae Lee (Seoul, KR)
Assignee: CHUNG ANG UNIVERSITY INDUSTRY ACADEMIC COOPERATION FOUNDATION
H10W40/73H10W40/254H10W40/40H10W76/15
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Quick Facts
Patent No.
US 12,740,414
App. No.
17/660,485
Granted
Sep 15, 2026
Kind
B2
Abstract

Disclosed is a semiconductor packaging. The semiconductor packing comprises a substrate on which a semiconductor device is arranged on a front surface; a channel member disposed on a rear surface of the substrate and forming a cooling flow path through which a refrigerant moves; and a porous diamond layer covering an outer surface of the channel member.

Claims (16)

1 . A semiconductor packaging comprising:

a substrate on which a semiconductor device is arranged on a front surface;

a channel member disposed on a rear surface of the substrate and forming a cooling flow path through which a refrigerant moves;

a porous diamond layer with a first pore size covering an outer surface of the channel member;

a porous layer with a second pore size stacked on the porous diamond layer and having wettability different from the porous diamond layer;

a refrigerant inlet and a refrigerant outlet arranged with the channel member in-between, and communicating with the cooling flow path;

a case in which the channel member is located inside; and

a manifold member disposed on one side of the channel member, the manifold member configured to be in parallel with a direction of movement of the refrigerant and to form a first transfer flow path and a second transfer flow path, the first transfer flow path connecting a refrigerant inlet with the cooling flow path and the second transfer flow path connecting a refrigerant outlet with the cooling flow path;

wherein one of the porous layer and the porous diamond layer is hydrophilic and an other of the porous layer and the porous diamond layer is hydrophobic;

wherein the second pore size of the porous layer is different from the first pore size of the porous diamond layer;

wherein the refrigerant inlet and the refrigerant outlet are formed in the case;

wherein the first transfer flow path has a first end open to communicate with the refrigerant inlet and a second end closed; and

wherein the second transfer flow path has a first end closed and a second end open to communicate with the refrigerant outlet.

2 . The semiconductor packaging of claim 1 , wherein the channel member comprises a plurality of pin members disposed to be spaced apart from each other and forming the cooling flow path therebetween.

3 . The semiconductor packaging of claim 1 , wherein a cross-sectional area of the first transfer flow path and a cross-sectional area of the second transfer flow path are each greater than a cross-sectional area of the cooling flow path.

4 . The semiconductor packaging of claim 1 , wherein the substrate and the channel member are formed with a same material.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2022
From: LEE, HYOUNGSOON; IN, JUNG BIN; KIM, YUNSEO; KONG, DAEYOUNG; KIM, KIWAN; LEE, JUNGBAE
To: CHUNG ANG UNIVERSITY INDUSTRY ACADEMIC COOPERATION FOUNDATION
Reel/Frame 059698/0052 →
Priority Claims (1)
KR 1020210081516 · Jun 23, 2021 · national
Continuity (1)
Related Publication 20220415751A1 · Dec 29, 2022
References Cited (16)
US 9257365B2 · Joshi · 2016 [cited by applicant]
US 10553519B2 · Morikawa et al. · 2020 [cited by applicant]
US 20030179596A1 · Joseph et al. · 2003 [cited by applicant]
US 20060012034A1 · Kadoya et al. · 2006 [cited by applicant]
US 20140252590A1 · Gohara · 2014 [cited by examiner]
US 20170287810A1 · Morikawa · 2017 [cited by examiner]
US 20200105644A1 · Teng · 2020 [cited by examiner]
US 20210084748A1 · Gil · 2021 [cited by examiner]
US 20210363016A1 · Alkhazraji · 2021 [cited by examiner]
JP 2006032490A · 2006 [cited by applicant]
JP 6502950B2 · 2019 [cited by applicant]
JP 2020507200A · 2020 [cited by applicant]
KR 102202443B1 · 2021 [cited by applicant]
K. Ueda, S. Aichi, H. Asano, Direct formation of graphene layers on diamond by high-temperature annealing with a Cu catalyst, Diamond and Related Materials, vol. 63, 2016, pp. 148-152, ISSN 0925-9635, https://doi.org/10… [cited by examiner]
Methods of porous diamond deposition on porous silicon (Year: 2001). [cited by examiner]
Office Action for Korean Patent Application No. 10-2021-0081516 filed on Jul. 23, 2021; Issue Date: Aug. 19, 2022; 7 pages (Original + English Translation). [cited by applicant]