Semiconductor package and method of manufacturing the semiconductor package
A semiconductor package includes a first semiconductor chip and a second semiconductor chip on the first semiconductor chip. The first semiconductor chip includes a first wiring layer on a first substrate, and a first passivation layer on the first wiring layer and that exposes at least portions of first bonding pads and a first test pad that are on the second wiring layer. The second semiconductor chip includes a second wiring layer on a second substrate and a second passivation layer on the second wiring layer and that exposes at least portions of third bonding pads and second test pad that are provided on the second wiring layer. The first bonding pads and respective ones of the third bonding pads are directly bonded to each other. The first passivation layer and the second passivation layer are directly bonded to each other.
1 . A semiconductor package, comprising:
a first semiconductor chip; and
a second semiconductor chip on the first semiconductor chip,
wherein the first semiconductor chip includes a first substrate, a plurality of through electrodes that penetrate the first substrate, a first wiring layer on a front side surface of the first substrate, first bonding pads on the first wiring layer and electrically connected to respective ones of the plurality of through electrodes, a first test pad on the first wiring layer, and a first passivation layer on the first wiring layer and that exposes at least portions of the first bonding pads and the first test pad,
wherein at least one first bonding pad of the first bonding pads and the first test pad are disposed adjacent to each other in the first passivation layer;
wherein the second semiconductor chip includes a second substrate, a second wiring layer on a front side surface of the second substrate, third bonding pads on the second wiring layer, a second test pad on the second wiring layer, and a second passivation layer on the second wiring layer and that exposes at least portions of the third bonding pads and the second test pad,
wherein the first bonding pads and respective ones of the third bonding pads are directly bonded to each other, and
wherein the first passivation layer and the second passivation layer are directly bonded to each other.
2 . The semiconductor package of claim 1 , wherein a distance of the first test pad from the front side surface of the first substrate is less than a distance of a first one of the first bonding pads from the front side surface of the first substrate.
3 . The semiconductor package of claim 1 , wherein the first and second test pads include aluminum or copper.
4 . The semiconductor package of claim 1 , wherein the first and second test pads include aluminum, and the first and second test pads are on the first and second wiring layers respectively.
5 . The semiconductor package of claim 4 , wherein the first and second test pads have a first thickness, and the first and third bonding pads have a second thickness greater than the first thickness.
6 . The semiconductor package of claim 1 , wherein the first and second test pads include copper, and the first and second test pads are provided in the first and second wiring layers respectively.
7 . The semiconductor package of claim 1 , wherein the first and second test pads have a first diameter, and the first and third bonding pads have a second diameter smaller than the first diameter.
8 . The semiconductor package of claim 1 , wherein the first and second passivation layers include silicon oxide, silicon nitride, or silicon carbon nitride.
9 . The semiconductor package of claim 1 , wherein at least a portion of the first test pad and at least a portion of the second test pad are directly bonded to each other.
10 . The semiconductor package of claim 9 , wherein the first test pad and the second test pad have a space therebetween that does not overlap the portion of the first test pad and the portion of the second test pad that are directly bonded to each other in a direction perpendicular to the first substrate.
11 . A semiconductor package, comprising:
a first semiconductor chip including a first substrate having a first surface and a second surface opposite to the first surface, a plurality of through electrodes that penetrate the first substrate, first bonding pads on the first surface of the first substrate and electrically connected to respective ones of the plurality of through electrodes, a first test pad on the first surface of the first substrate, and a first passivation layer on the first surface of the first substrate and that exposes at least portions of the first bonding pads and the first test pad; and
a second semiconductor chip on the first surface of the first semiconductor chip, the second semiconductor chip including a second substrate having a third surface and a fourth surface opposite to the third surface, third bonding pads on the third surface of the second substrate, a second test pad on the third surface of the second substrate, and a second passivation layer on the third surface of the second substrate and that exposes at least portions of the third bonding pads and the second test pad,
wherein at least one first bonding pad of the first bonding pads and the first test pad are disposed adjacent to each other in the first passivation layer;
wherein the first bonding pads and respective ones of the third bonding pads are directly bonded to each other,
wherein the first passivation layer and the second passivation layer are directly bonded to each other, and
wherein the first and second test pads have a first diameter, and the first and third bonding pads have a second diameter that is smaller than the first diameter.
12 . The semiconductor package of claim 11 , wherein the first and second test pads include aluminum or copper.
13 . The semiconductor package of claim 11 , wherein the first and second test pads include aluminum, and
wherein the first and second test pads are in the first and second passivation layers respectively.
14 . The semiconductor package of claim 13 , wherein the first and second test pads have a first thickness, and the first and third bonding pads have a second thickness greater than the first thickness.
15 . The semiconductor package of claim 11 , wherein the first and second test pads include copper, and the first and second test pads are in first and second wiring layers under the first and second passivation layers respectively.
16 . The semiconductor package of claim 11 , wherein the first and second passivation layers include silicon oxide, silicon nitride, or silicon carbon nitride.
17 . The semiconductor package of claim 11 , wherein at least a portion of the first test pad and at least a portion of the second test pad are directly bonded to each other.
18 . The semiconductor package of claim 17 , wherein the first test pad and the second test pad have a space therebetween that does not overlap the portion of the first test pad and the portion of the second test pad that are directly bonded to each other in a direction perpendicular to the first substrate.
19 . The semiconductor package of claim 11 , wherein the first test pad is electrically connected to a respective one of plurality of through electrodes, and the second test pad is electrically connected to a respective one of the third bonding pads.
20 . A semiconductor package, comprising:
a package substrate;
a first semiconductor chip including a first substrate having a first surface and a second surface opposite to the first surface, a plurality of through electrodes that penetrate the first substrate, first bonding pads on the first surface of the first substrate and electrically connected to respective ones of the plurality of through electrodes, second bonding pads on the second surface and electrically connected to respective ones of the plurality of through electrodes, a first test pad on the first surface of the first substrate, and a first passivation layer on the first surface of the first substrate and that exposes at least portions of the first bonding pads and the first test pad, wherein the first semiconductor chip is on the package substrate with conductive bumps therebetween that are on the second bonding pads; and
a second semiconductor chip including a second substrate having a third surface and a fourth surface opposite to the third surface, third bonding pads on the third surface of the second substrate, a second test pad on the third surface of the second substrate and a second passivation layer on the third surface of the second substrate and that exposes at least portions of the third bonding pads and the second test pad, wherein the second semiconductor chip is on the first semiconductor chip such that the third surface of the second semiconductor chip faces the first surface of the first semiconductor chip,
wherein at least one first bonding pad of the first bonding pads and the first test pad are disposed adjacent to each other in the first passivation layer;
wherein the first bonding pads and respective ones of the third bonding pads are directly bonded to each other, and
wherein the first passivation layer and the second passivation layer are directly bonded to each other.