Electronic device including stacked semiconductor chips and method of manufacturing the same
An electronic device and a manufacturing method are provided. The electronic device includes a first semiconductor chip, a second semiconductor chip and a third semiconductor chip. The second semiconductor chip is stacked on the first semiconductor chip, and is electrically connected to the first semiconductor chip by hybrid bonding. The third semiconductor chip is stacked on the second semiconductor chip, and is electrically connected to the second semiconductor chip through a plurality of bumps.
1 . An electronic device, comprising:
a first semiconductor chip, wherein the first semiconductor chip comprises a first lower structure, a first conductive structure disposed on the first lower structure, a first base portion disposed on the first conductive structure, a first upper structure disposed on the first base portion, and a first encapsulant disposed around the first lower structure, the first conductive structure, the first base portion, and the first upper structure to define a lateral surface of the first semiconductor chip at an outer surface of the first encapsulant;
a second semiconductor chip stacked on the first semiconductor chip, and electrically connected to the first semiconductor chip by hybrid bonding, wherein the second semiconductor chip comprises a second lower structure, a second conductive structure disposed on the second lower structure, a second base portion disposed on the second conductive structure, and a second upper structure disposed on the second base portion, wherein the second semiconductor chip has a lateral surface defined at an outer surface of the second base portion; and
a third semiconductor chip stacked on the second semiconductor chip, and electrically connected to the second semiconductor chip through a plurality of bumps, wherein the third semiconductor chip comprises a third lower structure, a third conductive structure disposed on the third lower structure, a third base portion disposed on the third conductive structure, a third upper structure disposed on the third base portion, and a third encapsulant disposed around the third lower structure, the third conductive structure, the third base portion, and the third upper structure to define a lateral surface of the third semiconductor chip at an outer surface of the third encapsulant;
wherein the second semiconductor chip is bonded between the first semiconductor chip and the third semiconductor chip at a position that the second lower structure of the second semiconductor chip is in contact with the first upper structure of the first semiconductor chip and the second upper structure of the second semiconductor chip is coupled to the third lower structure of the third semiconductor chip via the bumps;
wherein the lateral surface of the first semiconductor chip is aligned with the lateral surface of the second semiconductor chip and is aligned with the lateral surface of the third semiconductor chip;
wherein a width of the second lower structure of the second semiconductor chip is greater than a width of the first lower structure of the first semiconductor chip;
wherein a width of the first conductive structure is equal to the width of the first lower structure while a width of the second conductive structure is equal to the width of the second lower structure;
wherein a width of the third lower structure of the third semiconductor chip is equal to the width of the first lower structure of the first semiconductor chip.
2 . The electronic device of claim 1 , wherein a bottom surface of the second semiconductor chip contacts a top surface of the first semiconductor chip.
3 . The electronic device of claim 1 , wherein a bottom surface of the third semiconductor chip is spaced apart from a top surface of the second semiconductor chip.
4 . The electronic device of claim 3 , further comprising an underfill disposed between the bottom surface of the third semiconductor chip and the top surface of the second semiconductor chip to cover the plurality of bumps.
5 . The electronic device of claim 1 , wherein the first semiconductor chip further comprises a plurality of first conductive vias extending through the first base portion and electrically connecting to the first conductive structure, wherein a bottom surface of each of the first conductive vias is extended beyond a bottom surface of the first base portion and a top surface of each of the first conductive vias is coplanar with a top surface of the first base portion.
6 . The electronic device of claim 5 , wherein the second semiconductor chip further comprises a plurality of second conductive vias extending through the second base portion electrically connecting to the second conductive structure, wherein a bottom surface of each of the second conductive vias is extended beyond a bottom surface of the second base portion into the second conductive structure and a top surface of each of the second conductive vias is coplanar with a top surface of the second base portion.
7 . The electronic device of claim 6 , the third semiconductor chip further comprises a plurality of third conductive vias extending through the third base portion and electrically connecting to the third conductive structure, wherein a bottom surface of each of the third conductive vias is extended beyond a bottom surface of the third base portion into the third conductive structure, and a top surface of each of the third conductive via is coplanar with a top surface of the third base portion.
8 . The electronic device of claim 7 , wherein the first conductive vias extend into the first conductive structure.
9 . The electronic device of claim 7 , wherein the first upper structure includes a first upper dielectric layer and a plurality of first upper pads embedded in and exposed by the first upper dielectric layer, and the plurality of first upper pads contact the plurality of first conductive vias.
10 . The electronic device of claim 1 , further comprising a fourth semiconductor chip stacked on the third semiconductor chip, and electrically connected to the third semiconductor chip by hybrid bonding, wherein a lateral surface of the fourth semiconductor chip is aligned with the lateral surface of the third semiconductor chip, wherein the fourth semiconductor chip comprises a fourth lower structure, a fourth conductive structure disposed on the fourth lower structure, and a fourth base portion disposed on the fourth conductive structure, wherein the lateral surface of the fourth semiconductor chip is defined at an outer surface of the fourth base portion;
wherein a width of the fourth base portion of the fourth semiconductor chip is greater than the width of the third base portion of the third semiconductor chip.
11 . An electronic device, comprising:
a first assembly including a first semiconductor chip and a second semiconductor chip stacked on the first semiconductor chip and electrically connected to the first semiconductor chip by hybrid bonding; and
a second assembly including a third semiconductor chip and a fourth semiconductor chip stacked on the third semiconductor chip and electrically connected to the third semiconductor chip by hybrid bonding, wherein the second assembly is electrically connected to the first assembly through a plurality of bumps;
wherein the first semiconductor chip of the first assembly comprises a first base portion and a first encapsulant disposed around the first base portion;
wherein the second semiconductor chip of the first assembly comprises a second base portion;
wherein the third semiconductor chip of the second assembly comprises a third base portion and a third encapsulant disposed around the third base portion;
wherein the fourth semiconductor chip of the second assembly comprises a fourth base portion;
wherein a lateral surface of the first assembly is aligned with the lateral surface of the second assembly;
wherein an outer surface of the first encapsulant and an outer surface of the second base portion form the lateral surface of the first assembly;
wherein an outer surface of the third encapsulant and an outer surface of the fourth base portion form the lateral surface of the second assembly, such that the outer surface of the first encapsulant, the outer surface of the second base portion, the outer surface of the third encapsulant, and the outer surface of the fourth base portion are aligned with each other.
12 . The electronic device of claim 11 , wherein the plurality of bumps include a reflowable material.
13 . The electronic device of claim 11 , further comprising an underfill disposed between the second assembly and the first assembly and covering the plurality of bumps.
14 . The electronic device of claim 11 , wherein the second semiconductor chip and the first semiconductor chip are in face-to-face contact, the fourth semiconductor chip and the third semiconductor chip are in face-to-face contact, and the first assembly is spaced apart from the second assembly.
15 . The electronic device of claim 11 , wherein the first semiconductor chip further comprises:
a first conductive structure disposed on a first surface of the first base portion;
a first lower structure disposed on the first conductive structure; and
a first upper structure disposed on a second surface of the first base portion opposite to the first surface of the first base portion;
wherein the second semiconductor chip further comprises:
a second conductive structure disposed on the second base portion;
a second lower structure disposed on the second conductive structure; and
a second upper structure disposed on the second base portion;
wherein a width of the second base portion is greater than a width of the first base portion;
a width of the second conductive structure of the second semiconductor chip is greater than a width of the first conductive structure of the first semiconductor chip.
16 . The electronic device of claim 15 , wherein the first encapsulant is disposed around the first base portion, the first conductive structure, the first lower structure and the first upper structure, wherein the second semiconductor chip contacts the first encapsulant.
17 . The electronic device of claim 11 , wherein the third semiconductor chip further comprises:
a third conductive structure disposed on the third base portion;
a third lower structure disposed on the third conductive structure; and
a third upper structure disposed on the third base portion;
wherein the fourth semiconductor chip further comprises:
a fourth conductive structure disposed on the fourth base portion; and
a fourth lower structure disposed on the fourth conductive structure;
wherein a width of the fourth base portion is greater than a width of the third base portion;
wherein a width of the fourth conductive structure of the fourth semiconductor chip is greater than a width of the third conductive structure of the third semiconductor chip.
18 . The electronic device of claim 17 , wherein the third encapsulant is disposed around the third base portion, the third conductive structure, the third lower structure and the third upper structure, wherein the fourth semiconductor chip contacts the third encapsulant.