Phase shift of signals for RFI mitigation
An example of an apparatus may include signal circuitry to provide a first set of one or more signals and a second set of one or more signals for an electronic device, and radio frequency interference (RFI) mitigation circuitry coupled to one or more of the signal circuitry, the first set, and the second set to provide a delay between respective signals of the first and second sets based on RFI mitigation information associated with the respective signals. Other examples are disclosed and claimed.
1 . A memory device, comprising:
a circuit board;
memory on the circuit board; and
interface circuitry on the circuit board coupled to the memory to provide a plurality of output data read paths and a plurality of input data write paths for the memory, wherein the interface circuitry further comprises:
two or more clock signal pairs for the memory, and
radio frequency interference (RFI) mitigation circuitry coupled to the two or more clock signal pairs to provide a phase shift between respective clock signal pairs based on configuration information.
2 . The memory device of claim 1 , wherein the interface circuitry is further to:
determine the configuration information based on a resistance amount of one or more resistors populated on the circuit board.
3 . The memory device of claim 1 , wherein the interface circuitry is further to:
determine the configuration information from a data structure.
4 . The memory device of claim 3 , wherein the interface circuitry is further to:
program the configuration information in the data structure based on a resistance amount of one or more resistors populated on the circuit board.
5 . The memory device of claim 3 , wherein the data structure comprises a table that indicates respective amounts of delay to be applied to the respective clock signal pairs.
6 . The memory device of claim 5 , wherein an amount of delay to be stored in an entry of the table for a first clock signal pair of the two or more clock signal pairs is based on a distance between the first clock signal pair and a second clock signal pair of the two or more clock signal pairs.
7 . The memory device of claim 6 , wherein the second clock signal pair corresponds to a noise source and the first clock signal pair corresponds to a noise mitigator, and wherein the amount of delay to be stored in the entry of the table for the first clock signal pair corresponds to a phase shift between the first clock signal pair and the second clock signal pair for destructive interference between the noise source and the noise mitigator at an antenna location relative to a location of the first clock signal pair and the second clock signal pair.
8 . The memory device of claim 7 , wherein clock signal pairs to be designated as noise sources are to be located closer to the antenna location relative to clock signal pairs to be designated as noise mitigators.
9 . The memory device of claim 1 , wherein one or more of the two or more clock signal pairs includes a conductive trace on an outermost layer of the circuit board.
10 . A system, comprising:
a controller; and
a memory device coupled to the controller, the memory device comprising a circuit board, memory on the circuit board, and two or more clock signal pairs for the memory,
wherein the controller is to apply a phase shift between respective clock signal pairs of the two or more clock signal pairs for the memory based on radio frequency interference (RFI) mitigation information.
11 . The system of claim 10 , wherein the controller is further to:
determine the RFI mitigation information based on a resistance amount of one or more resistors populated on the circuit board.
12 . The system of claim 10 , wherein the controller is further to:
determine the RFI mitigation information from a data structure.
13 . The system of claim 12 , wherein the controller is further to:
program the RFI mitigation information in the data structure based on a resistance amount of one or more resistors populated on the circuit board.