3D IC structure
An IC structure includes a first memory stack including a plurality of semiconductor die. The plurality of semiconductor memory dies horizontally separate with each other, wherein each semiconductor die includes a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads located on the first sidewall and arranged in multiple rows or two dimensions. The area of the bottom surface or the top surface is larger than that of any sidewall. A first part of the plurality of edge pads is located within a upper portion of the first sidewall of the semiconductor die, a second part of the plurality of edge pads is located within a lower portion of the first sidewall of the semiconductor die.
1 . An IC structure comprising:
a first memory stack comprising:
a plurality of semiconductor dies horizontally separate from each other, wherein each semiconductor die comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads located on the first sidewall and arranged in multiple rows or two dimensions; wherein an area of the bottom surface or the top surface is larger than that of any of the first sidewall, the second sidewall, the third sidewall and the fourth sidewall;
wherein the plurality of edge pads is located within a central portion of the first sidewall of the semiconductor die.
2 . The IC structure of claim 1 , wherein each semiconductor die is a composite die comprising a memory die and a dummy die; wherein a first part of the plurality of edge pads is located on a sidewall of the memory die, and a second part of the plurality of edge pads is located on a sidewall of the dummy die.
3 . The IC structure of claim 2 , wherein the memory die further includes a plurality of signal pads located within a seal ring, a first part of the plurality of signal pads are electrically connected to the first part of the plurality of edge pads through a first RDL structure of the memory die, and a second part of the plurality of signal pads are electrically connected to the second part of the plurality of edge pads through a second RDL structure of the dummy die and the first RDL structure of the memory die, wherein the first RDL structure is faced to the second RDL structure.
4 . The IC structure of claim 3 , wherein the first part of the plurality of edge pads is exposed from a sidewall of the first RDL structure of the memory die, and the second part of the plurality of edge pads is exposed from a sidewall of the second RDL structure of the dummy die, wherein the central portion of the first sidewall of the semiconductor die includes the sidewall of the first RDL structure of the memory die and the sidewall of the second RDL structure of the dummy die.
5 . The IC structure of claim 2 , wherein the dummy die is an upward extending thermal conductivity layer next to the memory die, and a thermal conductivity of the upward extending thermal conductivity layer is higher than that of SiO2.
6 . The IC structure of claim 5 , wherein the IC structure further comprises:
a laterally extending thermal conductivity layer covering each second sidewall of the plurality of semiconductor dies and thermally coupling to the upward extending thermal conductivity layer, wherein the laterally extending thermal conductivity layer is opposite to the first sidewalls of the plurality of semiconductor dies;
wherein the thermal conductivity of the laterally extending thermal conductivity layer is higher than that of SiO2.
7 . The IC structure of claim 1 , wherein the IC structure further comprises:
a logic die with memory controller under the first memory stack and electrically connected to the plurality of edge pads of each semiconductor die of the first memory stack;
a logic die with processor circuit disposed over and electrically connected to the logic die with memory controller; and
a packaging substrate under and electrically connected to the logic die with memory controller.
8 . The IC structure of claim 7 , further comprising:
a second memory stack comprising:
a plurality of semiconductor dies horizontally separate from each other, wherein each semiconductor die comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads located on the first sidewall and arranged in multiple rows or two dimensions; wherein the plurality of edge pads of each semiconductor die of the second memory stack is electrically connected to the logic die with memory controller;
wherein the first memory stack and the second memory stack are horizontally spaced apart from the logic die with processor circuit, and are positioned over the logic die with memory controller;
wherein the first memory stack and the second memory stack are disposed along one side of the logic die with processor circuit, or are disposed along two sides of the logic die with processor circuit respectively.
9 . The IC structure of claim 1 , wherein the IC structure further comprises:
a logic die with memory controller and processor circuit under the first memory stack and electrically connected to the plurality of edge pads of each semiconductor die of the first memory stack; and
a packaging substrate under and electrically connected to the logic die with memory controller and processor.
10 . The IC structure of claim 9 , further comprising:
a second memory stack comprising:
a plurality of semiconductor dies horizontally separate from each other, wherein each semiconductor die comprises a top surface, a bottom surface opposite to the top surface, and four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads located on the first sidewall and arranged in multiple rows or two dimensions; wherein the plurality of edge pads of each semiconductor die of the second memory stack is electrically connected to the logic die with memory controller and processor circuit;
wherein the first memory stack and the second memory stack are horizontally spaced apart from each other, and are positioned over the logic die with memory controller and processor circuit.
11 . The IC structure of claim 1 , wherein there is no TSV in each semiconductor die.