High memory density, high input/output bandwidth logic-memory structure and architecture
A chip stack structure includes a logic chip having an active device surface, and memory slices of a memory unit vertically aligned such that a surface of the memory slices is oriented perpendicular to the active device surface of the logic chip. The chip stack structure also includes wiring patterned on an upper surface of the memory slices, the wiring electrically connecting memory leads of the memory slices to logic grids corresponding to logic grid connections of the logic chip.
1. A chip stack structure, comprising:
a logic chip having an active device surface;
a plurality of memory slices of a memory unit, the plurality of memory slices vertically aligned such that an active device surface of the plurality of memory slices is oriented perpendicular to the active device surface of the logic chip; and
wiring patterned on an upper surface of the plurality of memory slices, the wiring configured to correct distortions occurring from a slicing and assembly process of the memory slices, the wiring electrically connecting memory leads of the plurality of memory slices to logic grids corresponding to logic grid connections of the logic chip.
2. The chip stack structure of claim 1 , wherein a portion of the upper wiring surface of the plurality of memory slices includes fanout wiring, and another portion of the upper wiring surface of the plurality of memory slices includes active electrical connections to and from the logic chip on the logic grid connections.
3. The chip stack structure of claim 2 , wherein the portion of the upper wiring surface of the plurality of memory slices that includes the fanout wiring includes two regions, wherein each of the two regions corrects for the distortions in a direction that is parallel to the active device surface of the logic chip.
4. The chip stack structure of claim 3 , wherein the fanout wiring in the first region is slanted to correct for the distortions, and the fanout wiring in the second region is oriented in a plane on an upper part of the plurality of memory slices and is perpendicular to the active device surface of the plurality of memory slices.
5. The chip stack structure of claim 1 , wherein the plurality of memory slices each includes a tolerance region disposed on opposing ends of the plurality of memory slices.
6. A method of identifying and correcting distortions in a stacked memory unit resulting from a memory stack building process for a logic-memory device, the method comprising:
scanning the stacked memory unit, locating a position of each of a plurality of memory slices relative to a position of others of the plurality of memory slices resulting from the scanning, and calculating a skew value representing a difference between a current position of leads of the plurality of memory slices and a pre-planned position of the leads; and
responsive to determining a distortion exists from the scanning, correcting the distortion using the skew value by laser direct writing a connection between each of a plurality of logic grid connections and corresponding leads.
7. The method of claim 6 , wherein the laser direct writing corrects the distortion between the logic grid connections and the corresponding leads within a single memory slice.
8. The method of claim 6 , further comprising:
configuring input/output connections on a lower surface of each of the plurality of memory slices, the input/output connections configured to align with input/output interconnect components of the logic-memory device; and
responsive to determining the distortion exists from the scanning, correcting the distortion using the skew value by laser direct writing a connection between each of the input/output connections and corresponding interconnect components.
9. The method of claim 6 , wherein the distortion is identified using an optical laser.
10. The method of claim 6 , wherein the connection is written using direct laser lithography.
11. The method of claim 6 , wherein the logic-memory device is a four-dimensional integration device.
12. The method of claim 6 , wherein the distortion occurs along a first axis, and the skew value represents a shift misalignment among the plurality of memory slices during a stacking step in the memory stack building process.
13. The method of claim 6 , wherein the distortion occurs along a second axis, and the skew value represents a variation in thickness of the plurality of memory slices during a memory wafer thinning step in the memory stack building process.
14. The method of claim 6 , wherein the correcting is implemented across multiple lead layers.
15. A chip stack structure, comprising:
a crossbar chip having an active device surface;
a plurality of combined memory and processor slices of a processor memory unit vertically aligned such that an active device surface of the plurality of the combined memory and processor slices is oriented perpendicular to the active device surface of the crossbar chip, wherein electrical interconnects are formed between devices on the active device surface of the crossbar chip and devices on the active surface of the plurality of combined memory and processor slices by connections on an upper wiring surface of the plurality of combined memory and processor slices.
16. The chip stack structure of claim 15 , wherein a portion of the upper wiring surface of the plurality of combined memory and processor slices includes fanout wiring connections, and another portion of the upper wiring surface of the plurality of combined memory and processor slices includes active electrical connections to and from the crossbar chip.
17. The chip stack structure of claim 16 , wherein the portion of the upper wiring surface of the plurality of combined memory and processor slices that includes the fanout wiring further includes two regions, wherein each of the two regions corrects for the distortions in a direction that is parallel to the active device surface of the logic chip.
18. The chip stack structure of claim 17 , wherein the fanout wiring in the first region is slanted to correct for the distortions, and the fanout wiring in the second region is oriented in a plane on an upper part of the plurality of combined memory and processor slices and is perpendicular to the active device surface of the plurality of combined memory and processor slices.
19. The chip stack structure of claim 17 , wherein the plurality of combined memory and processor slices each includes a tolerance region disposed on opposing ends of the combined memory and processor slices.