Threshold voltage modulation by gate height variation
Semiconductor devices and methods of forming the same are provided. A semiconductor structure includes a substrate, a first active region, a second active region and a third active region over the substrate, a first gate structure over a channel region of the first active region, a second gate structure over a channel region of the second active region, a third gate structure over a channel region of the third active region, a first cap layer over the first gate structure, a second cap layer over the second gate structure, and a third cap layer over the third gate structure. A height of the second gate structure is smaller than a height of the first gate structure or a height of the third gate structure.
1 . A method, comprising:
receiving a workpiece comprising:
a first active region, a second active region and a third active region over a substrate,
a first gate structure over a channel region of the first active region,
a second gate structure over a channel region of the second active region, and
a third gate structure over a channel region of the third active region;
selectively recessing the second gate structure;
after the selectively recessing, recessing the first gate structure, the second gate structure, and the third gate structure to form a first gate recess over the first gate structure, a second gate recess over the second gate structure, and a third gate recess over the third gate structure;
after the recessing, depositing a dielectric cap layer over the first gate recess, the second gate recess, and the third gate recess; and
after the depositing, planarizing the workpiece to reduce a thickness of the dielectric cap layer,
wherein the first gate structure comprises a gate dielectric layer and a first work function layer over the gate dielectric layer,
wherein the second gate structure comprises the gate dielectric layer and a second work function layer over the gate dielectric layer,
wherein the third gate structure comprises the gate dielectric layer and a third work function layer over the gate dielectric layer,
wherein a composition of the third work function layer is different from a composition of the first work function layer or a composition of the second work function layer,
wherein each of the first work function layer and the second work function layer is an n-type work function metal layer,
wherein the third work function layer is a p-type work function metal layer.
2 . The method of claim 1 , wherein the selectively recessing the second gate structure comprises:
forming a patterned photoresist layer over the first gate structure and the third gate structure while the second gate structure is exposed; and
etching the second gate structure using the patterned photoresist layer as an etch mask.
3 . The method of claim 1 ,
wherein the n-type work function metal layer comprises TiAlC, TaAlC, silicon-doped TiAlC, or silicon-doped TaAlC,
wherein the p-type work function metal layer comprises TiN, TaN, WCN, TiSiN, or TaSiN.
4 . The method of claim 1 , wherein the dielectric cap layer comprises silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, aluminum oxide, zirconium silicate, hafnium silicate, hafnium oxide, or zirconium oxide.
5 . The method of claim 1 , further comprising:
before the depositing of the dielectric cap layer, depositing a selective metal layer over the first gate recess, the second gate recess, and the third gate recess,
wherein the selective metal layer comprises Ti, Ta, Al, Mo, W, Co, Cu, Ru, Mo, or Zr,
wherein each of the first gate structure, the second gate structure and the third gate structure are disposed between two gate spacers,
wherein the selectively recessing and the recessing etches the two gate spacers at a slower rate such that top surfaces of the two gate spacers are higher than top surfaces of the first work function layer, the second work function layer and the third work function layer,
wherein, after the depositing of the selective metal layer, a top surface of the selective metal layer is lower than the top surfaces of the two gate spacers.
6 . The method of claim 1 , wherein the recessing comprises use of BCl 3 , Cl 2 , HBr, SiCl 4 , O 2 , N 2 , CF 4 , or SF 6 .
7 . The method of claim 6 , wherein the recessing comprises a power between about 300 W and about 1800 W.
8 . The method of claim 6 , wherein the recessing comprises a bias power between about OW and about 100 W.
9 . The method of claim 1 , wherein a depth of the second gate recess is greater than a depth of the first gate recess or a depth of the third gate recess.
10 . A method, comprising:
receiving a workpiece comprising:
a first active region, a second active region and a third active region over a substrate,
a first gate structure over a channel region of the first active region,
a second gate structure over a channel region of the second active region,
a third gate structure over a channel region of the third active region, and
a pair of gate spacers disposed along sidewalls of each of the first gate structure, the second gate structure, and the third gate structure;
selectively recessing the second gate structure to form a pilot recess;
after the selectively recessing of the second gate structure, recessing the first gate structure, the second gate structure and the third gate structure to form a first gate recess over the first gate structure, extend the pilot recess to form a second gate recess over the second gate structure, and form a third gate recess over the third gate structure, wherein the recessing etches the pair of gate spacers at a slower rate such that top surfaces of the pair of gate spacers are higher than top surfaces of the first gate structure, the second gate structure and the third gate structure;
depositing a selective metal layer over the first gate recess, the second gate recess and the third gate recess such that a top surface of the selective metal layer is lower than the top surfaces of the pair of gate spacers;
depositing a dielectric cap layer over the selective metal layer; and
after the depositing, planarizing the workpiece,
wherein the first gate structure comprises a gate dielectric layer and a first work function layer over the gate dielectric layer,
wherein the second gate structure comprises the gate dielectric layer and a second work function layer over the gate dielectric layer,
wherein the third gate structure comprises the gate dielectric layer and a third work function layer over the gate dielectric layer,
wherein each of the first work function layer and the second work function layer is an n-type work function metal layer,
wherein the third work function layer is a p-type work function metal layer.
11 . The method of claim 10 , wherein a depth of the second gate recess is greater than a depth of the first gate recess or a depth of the third gate recess.
12 . The method of claim 11 , wherein the depth of the first gate recess is similar to the depth of the third gate recess.
13 . The method of claim 10 , wherein the selectively recessing of the second gate structure comprises:
forming a first patterned photoresist layer over the first gate structure and the third gate structure while the second gate structure is exposed; and
etching the second gate structure using the first patterned photoresist layer as an etch mask.
14 . The method of claim 10 ,
wherein the n-type work function metal layer comprises TiAlC, TaAlC, silicon-doped TiAlC, or silicon-doped TaAlC,
wherein the p-type work function metal layer comprises TiN, TaN, WCN, TiSiN, or TaSiN.
15 . The method of claim 10 , wherein the dielectric cap layer comprises silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, aluminum oxide, zirconium silicate, hafnium silicate, hafnium oxide, or zirconium oxide.
16 . The method of claim 10 , wherein the selective metal layer comprises Ti, Ta, Al, Mo, W, Co, Cu, Ru, Mo, or Zr.
17 . The method of claim 10 , wherein the selective metal layer comprises a thickness between about 1 nm and about 8 nm.
18 . A method, comprising:
receiving a workpiece comprising:
a first active region, a second active region and a third active region over a substrate,
a gate dielectric layer over a channel region of the first active region, a channel region of the second active region, and a channel region of the third active region,
a first source/drain feature over a source/drain region of the first active region, a second source/drain feature over a source/drain region of the second active region, and a third source/drain feature over a source/drain region of the third active region, and
an interlayer dielectric (ILD) layer over the first source/drain feature, the second source/drain feature, and the third source/drain feature;
depositing a dipole inducing layer over the gate dielectric layer and the ILD layer such that the dipole inducing layer interfaces a top surface of the ILD layer;
after the depositing of the dipole inducing layer, performing an anneal process to the workpiece;
after the performing of the anneal process, removing excess of the dipole inducing layer;
after the removing, depositing a gate electrode layer over the gate dielectric layer over the channel region of the first active region, the channel region of the second active region, and the channel region of the third active region;
selectively recessing the gate electrode layer and the gate dielectric layer over the channel region of the second active region to form a pilot recess;
after the selectively recessing, recessing the gate electrode layer and the gate dielectric layer over the channel region of the first active region, the channel region of the second active region, and the channel region of the third active region to form a first gate recess, a second gate recess, and form a third gate recess, respectively;
depositing a dielectric cap layer over the first gate recess, the second gate recess and the third gate recess; and
after the depositing, planarizing the workpiece,
wherein the dipole inducing layer comprises aluminum oxide, zirconium oxide, zinc oxide, yttrium oxide, or lanthanum oxide.
19 . The method of claim 18 , wherein a depth of the second gate recess is greater than a depth of the first gate recess or a depth of the third gat recess.
20 . The method of claim 18 , wherein the dielectric cap layer comprises silicon oxide, silicon nitride, silicon carbonitride, silicon oxycarbonitride, silicon oxycarbide, aluminum oxide, zirconium silicate, hafnium silicate, hafnium oxide, or zirconium oxide.