IP Library › Granted Patent US 12,745,439
Granted Patent B2
US 12,745,439 · App. 18/539,385 · Granted Sep 22, 2026

Frontside-to-backside connection with cut for stacked transistor

Inventors: Nicholas Anthony Lanzillo (Wynantskill, NY); Koichi Motoyama (Clifton Park, NY); Ruilong Xie (Niskayuna, NY); James P Mazza (Saratoga Springs, NY)
Assignee: International Business Machines Corporation
H10D62/151H10D84/013H10D84/0149H10D84/038H10D84/83H10W20/089H10W20/43
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Quick Facts
Patent No.
US 12,745,439
App. No.
18/539,385
Granted
Sep 22, 2026
Kind
B2
Abstract

Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a device layer having a first top source/drain (S/D), a second top S/D, a first bottom S/D, and a second bottom S/D. The semiconductor structure may further include a first direct back side contact connected to the first bottom S/D, a second direct back side contact connected to the second bottom S/D, and a double via. The double via may include a first half connecting a front side of the device layer to the first direct back side contact, and a second half connecting the front side to the second direct back side contact. The double via may also include a dividing cut splitting the first half of the double via from the second half of the double via.

Claims (35)

1 . A semiconductor structure, comprising:

a device layer comprising a first top source/drain (S/D), a second top S/D, a first bottom S/D, and a second bottom S/D;

a first direct back side contact connected to the first bottom S/D;

a second direct back side contact connected to the second bottom S/D;

a double via comprising:

a first half connecting a front side of the device layer to the first direct back side contact; and

a second half connecting the front side to the second direct back side contact; and

a dividing cut splitting the first half of the double via from the second half of the double via.

2 . The semiconductor structure of claim 1 , wherein the dividing cut comprises a taper from the front side to a back side.

3 . The semiconductor structure of claim 1 , wherein the dividing cut comprises a taper from a back side to the front side.

4 . The semiconductor structure of claim 1 , wherein the dividing cut splits the first direct back side contact from the second direct back side contact.

5 . The semiconductor structure of claim 1 , wherein the first half directly contacts the first S/D.

6 . The semiconductor structure of claim 1 , wherein the dividing cut comprises a first section tapered from the front side and a second section tapered from a back side.

7 . The semiconductor structure of claim 1 , wherein the dividing cut comprises a self-aligned dividing cut.

8 . A method of fabricating a semiconductor structure, comprising:

forming a first top source/drain (S/D), a second top S/D, a first bottom S/D, and a second bottom S/D in a stacked transistor architecture;

forming a double via between the first top S/D and the second top S/D, and between the first bottom S/D and the second bottom S/D;

forming a dividing cut to split the double via into i) a first half electrically connected between the first bottom S/D and a front side of the semiconductor structure and ii) a second half electrically connected between the second bottom S/D and the front side.

9 . The method of claim 8 , wherein the dividing cut is formed from the front side.

10 . The method of claim 8 , wherein the dividing cut is formed from a back side.

11 . The method of claim 8 , further comprising:

forming a direct back side contact; and

splitting the first direct back side contact from the second direct back side contact with the dividing cut.

12 . The method of claim 8 , wherein forming the double via comprises etching an interlayer dielectric from the first bottom S/D and depositing the double via directly onto the first bottom S/D.

13 . The method of claim 8 , wherein forming the dividing cut comprises forming a first section tapered from the front side and forming a second section tapered from a back side.

14 . A semiconductor structure, comprising:

a double via comprising:

a first half electrically connected between a front side of a device layer and a first bottom source/drain (S/D) in a stacked transistor architecture; and

a second half electrically connected between the front side and a second bottom S/D in the stacked transistor architecture, wherein the first half of the double via is split from the second half of the double via by a dividing cut.

15 . The semiconductor structure of claim 14 , wherein the cut comprises a taper from the front side to a back side.

16 . The semiconductor structure of claim 14 , wherein the dividing cut comprises a taper from a back side to the front side.

17 . The semiconductor structure of claim 16 , wherein the dividing cut also splits i) a first direct back side contact between the first bottom S/D and the first half from ii) a second direct back side contact between the second bottom S/D and the second half.

18 . The semiconductor structure of claim 14 , wherein the first half directly contacts the first S/D.

19 . The semiconductor structure of claim 18 , wherein the dividing cut comprises a first section tapered from the front side and a second section tapered from a back side.

20 . The semiconductor structure of claim 14 , wherein the dividing cut comprises a self-aligned dividing cut.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2023
From: LANZILLO, NICHOLAS ANTHONY; MOTOYAMA, KOICHI; XIE, RUILONG; MAZZA, JAMES P
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 065866/0689 →
Continuity (1)
Related Publication 20250203974A1 · Jun 19, 2025
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