Semiconductor transistor structure and fabrication method thereof
A semiconductor transistor structure includes a semiconductor substrate having an active area and a trench isolation region surrounding the active area; a first inter-layer dielectric (ILD) layer covering the semiconductor substrate; a metal gate embedded in the first ILD layer and overlying the active area and the trench isolation region, wherein the metal gate comprises a first portion disposed directly above the active area and a second portion disposed directly above the trench isolation region, wherein the first portion is thicker than the second portion; a hard mask layer disposed on the second portion; and a gate dielectric layer disposed between the first portion of the metal gate and the active area.
1 . A semiconductor transistor structure, comprising:
a semiconductor substrate having an active area and a trench isolation region surrounding the active area;
a first inter-layer dielectric (ILD) layer covering the semiconductor substrate;
a metal gate embedded in the first ILD layer and overlying the active area and the trench isolation region, wherein the metal gate comprises a first portion disposed directly above the active area and a second portion disposed directly above the trench isolation region, wherein the first portion is thicker than the second portion;
a hard mask layer disposed on the second portion of the metal gate;
a gate dielectric layer disposed between the first portion of the metal gate and the active area;
a source doping region disposed on a first side of the metal gate;
a drain doping region disposed on an opposing second side of the metal gate
a second inter-layer dielectric (ILD) layer covering the first ILD layer, the hard mask layer, and the metal gate; and
a contact plug embedded in the second ILD layer and extending into the hard mask layer to electrically contact with the second portion of the metal gate.
2 . The semiconductor transistor structure according to claim 1 , wherein the hard mask layer comprises a silicon nitride layer.
3 . The semiconductor transistor structure according to claim 1 , wherein the metal gate comprises a metal filling layer and a work function metal (WFM) layer.
4 . The semiconductor transistor structure according to claim 3 , wherein the metal filling layer comprises a tungsten layer.
5 . The semiconductor transistor structure according to claim 3 , wherein the hard mask layer is in direct contact with the metal filling layer.
6 . The semiconductor transistor structure according to claim 1 , wherein the hard mask layer has a top surface that is coplanar with a top surface of the first portion of the metal gate.
7 . The semiconductor transistor structure according to claim 1 wherein the contact plug comprises tungsten.
8 . The semiconductor transistor structure according to claim 1 , wherein the second portion of the metal gate has a width greater than or equal to 0.07 micrometers.
9 . A method of forming a semiconductor transistor structure, comprising:
providing a semiconductor substrate having an active area and a trench isolation region surrounding the active area;
forming a first inter-layer dielectric (ILD) layer covering the semiconductor substrate;
forming a metal gate embedded in the first ILD layer and overlying the active area and the trench isolation region, wherein the metal gate comprises a first portion disposed directly above the active area and a second portion disposed directly above the trench isolation region, wherein the first portion is thicker than the second portion;
forming a source doping region on a first side of the metal gate;
forming a drain doping region on an opposing second side of the metal gate;
forming a hard mask layer on the second portion of the metal gate; and
forming a gate dielectric layer between the first portion of the metal gate and the active area;
forming a second inter-layer dielectric (ILD) layer covering the first ILD layer, the hard mask layer, and the metal gate; and
forming a contact plug embedded in the second ILD layer and extending into the hard mask layer to electrically contact with the second portion of the metal gate.
10 . The method according to claim 9 , wherein the hard mask layer comprises a silicon nitride layer.
11 . The method according to claim 9 , wherein the metal gate comprises a metal filling layer and a work function metal (WFM) layer.
12 . The method according to claim 11 , wherein the metal filling layer comprises a tungsten layer.
13 . The method according to claim 11 , wherein the hard mask layer is in direct contact with the metal filling layer.
14 . The method according to claim 9 , wherein the hard mask layer has a top surface that is coplanar with a top surface of the first portion of the metal gate.
15 . The method according to claim 9 wherein the contact plug comprises tungsten.
16 . The method according to claim 9 , wherein the second portion of the metal gate has a width greater than or equal to 0.07 micrometers.