Memory device and memory system
A memory device includes at least one bank including at least a first sub-bank and a second sub-bank disposed in a wordline direction. The first sub-bank may include a normal data region connected to a plurality of first wordlines and storing normal data, the second sub-bank may include a metadata region connected to a plurality of second wordlines and storing metadata corresponding to the normal data, the plurality of first wordlines may match the plurality of second wordlines to form a plurality of wordline pairs, and the first sub-bank and the second sub-bank may share a row hammer region storing a number of access times to the plurality of wordline pairs.
1 . A memory device comprising at least one bank, the at least one bank comprising:
a first sub-bank comprising:
a plurality of first wordlines extending in a first direction; and
a normal data region connected to the plurality of first wordlines, the normal data region configured to store normal data,
a second sub-bank comprising:
a plurality of second wordlines extending in the first direction; and
a metadata region connected to the plurality of second wordlines, the metadata region configured to store metadata of the normal data,
wherein the plurality of first wordlines and the plurality of second wordlines are matched to form a plurality of wordline pairs, and
wherein the at least one bank further comprises a row hammer region shared by the first sub-bank and the second sub-bank, the row hammer region configured to store a number of times the plurality of wordline pairs are accessed.
2 . The memory device of claim 1 ,
wherein the row hammer region comprises:
a plurality of count cells configured to store the number of times the plurality of wordline pairs are accessed; and
a plurality of count parity cells configured to store count parity data corresponding to the plurality of count cells, and
wherein the plurality of count cells and the plurality of count parity cells are disposed in the first sub-bank.
3 . The memory device of claim 1 ,
wherein the row hammer region comprises:
a plurality of count cells configured to store the number of times the plurality of wordline pairs are accessed; and
a plurality of count parity cells configured to store count parity data corresponding to the plurality of count cells, and
wherein the plurality of count cells are disposed in the first sub-bank, and the plurality of count parity cells are disposed in the second sub-bank.
4 . The memory device of claim 1 ,
wherein the row hammer region comprises:
a plurality of count cells configured to store the number of times the plurality of wordline pairs are accessed; and
a plurality of count parity cells configured to store count parity data corresponding to the plurality of count cells, and
wherein the plurality of count cells are disposed in both the first sub-bank and the second sub-bank, and the plurality of count parity cells are disposed in the second sub-bank.
5 . The memory device of claim 1 , wherein
the first sub-bank and the second sub-bank correspond to different global input/output lines.
6 . The memory device of claim 5 , wherein, in response to a read operation being performed on the normal data stored in the normal data region,
the normal data is output through a first global input/output line corresponding to the first sub-bank, and the metadata is output through a second global input/output line corresponding to the second sub-bank simultaneously with the normal data.
7 . The memory device of claim 1 , wherein
the normal data region comprises a plurality of normal regions respectively connected to the plurality of first wordlines,
the metadata region comprises a plurality of meta regions respectively connected to the plurality of second wordlines and matching the plurality of normal regions, and
the row hammer region comprises a plurality of row count regions disposed in the first sub-bank and respectively connected to the plurality of first wordlines.
8 . The memory device of claim 7 , wherein
each normal region of the plurality of normal regions corresponds to a plurality of first column select lines and a plurality of second column select lines, and
a ratio of a number of the plurality of first column select lines and a number of the plurality of second column select lines is 8:1.
9 . The memory device of claim 7 , wherein
each normal region of the plurality of normal regions corresponds to a plurality of first column select lines and a plurality of second column select lines,
a ratio of a number of the plurality of first column select lines and a number of the plurality of second column select lines is 16:1.
10 . The memory device of claim 1 , wherein
the normal data region comprises a plurality of normal regions respectively connected to the plurality of first wordlines,
the metadata region comprises a plurality of meta regions respectively connected to the plurality of second wordlines and matching the plurality of normal regions, and
the row hammer region comprises:
a plurality of first sub row count regions disposed in the first sub-bank and respectively connected to the plurality of first wordlines; and
a plurality of second sub row count regions disposed in the second sub-bank and respectively connected to the plurality of second wordlines.
11 . The memory device of claim 1 , further comprising:
a row hammer management circuit configured to manage the number of times the plurality of wordline pairs are accessed,
wherein
the row hammer management circuit is configured to read, from the row hammer region, count data corresponding to a selected wordline pair among the plurality of wordline pairs, update the read count data, and re-store the updated count data in the row hammer region in response to activation of the selected wordline pair.
12 . The memory device of claim 11 , further comprising:
an error correction code (ECC) engine configured to read count parity data corresponding to the count data from the row hammer region and perform a decoding operation on the count data using the count parity data.
13 . The memory device of claim 1 , wherein
the first sub-bank further comprises a metadata region connected to the plurality of first wordlines, the metadata region being configured to store metadata, and
the second sub-bank further comprises a normal data region connected to the plurality of second wordlines, the normal data region being configured to store normal data.
14 . A memory device comprising at least one bank, the at least one bank comprising:
a first sub-bank comprising:
a plurality of first wordlines extending in a wordline direction; and
a plurality of first mats; and
a second sub-bank comprising:
a plurality of second wordlines; and
a plurality of second mats;
a first row decoder connected to the first sub-bank through the plurality of first wordlines;
a plurality of first column select lines;
a plurality of second column select lines;
a first column decoder connected to the first sub-bank through the plurality of first column select lines;
a second row decoder connected to the second sub-bank through the plurality of second wordlines; and
a second column decoder connected to the second sub-bank through the plurality of second column select lines,
wherein
each mat of the plurality of first mats comprises a normal data region connected to a portion of the plurality of first wordlines, the normal data region configured to store normal data,
each mat of the plurality of second mats comprises a metadata region connected to a portion of the plurality of second wordlines, the metadata region configured to store metadata corresponding to the normal data,
the plurality of first wordlines and the plurality of second wordlines are matched to form a plurality of wordline pairs, and
at least one of the plurality of first mats included in the first sub-bank comprises one or more count cells configured to store count data, the count data comprising a number of accesses to the plurality of wordline pairs.
15 . The memory device of claim 14 , wherein
at least one of the plurality of first mats included in the first sub-bank comprises one or more count parity cells configured to store count parity data for the count data.
16 . The memory device of claim 15 , wherein
a ratio of a number of the one or more count cells and a number of the count parity cells is 2:1.
17 . The memory device of claim 14 , wherein
at least one of the plurality of second mats included in the second sub-bank comprises one or more count parity cells configured to store count parity data for the count data.
18 . The memory device of claim 14 , wherein
the first sub-bank and the second sub-bank correspond to different global input/output lines.
19 . The memory device of claim 14 , wherein, in response to a read operation being performed on the normal data stored in the normal data region,
the normal data is output through a first global input/output line corresponding to the first sub-bank, and the metadata is output through a second global input/output line corresponding to the second sub-bank simultaneously with the normal data.
20 . A memory system comprising:
a memory device comprising at least one bank, the at least one bank comprising:
a first sub-bank comprising:
a plurality of first wordlines; and
a normal data region connected to the plurality of first wordlines; and
a second sub-bank comprising:
a plurality of second wordlines; and
a metadata region connected to the plurality of second wordlines, the metadata region being configured to store metadata corresponding to the normal data; and
a memory controller configured to control the memory device,
wherein the plurality of first wordlines and the plurality of second wordlines are matched to form a plurality of wordline pairs, and
wherein the at least one bank further comprises a row hammer region shared by the first sub-bank and the second sub-bank, the row hammer region configured to store a number of accesses to the plurality of wordline pairs.